JPS5619250A - Information transmitting system - Google Patents
Information transmitting systemInfo
- Publication number
- JPS5619250A JPS5619250A JP9418279A JP9418279A JPS5619250A JP S5619250 A JPS5619250 A JP S5619250A JP 9418279 A JP9418279 A JP 9418279A JP 9418279 A JP9418279 A JP 9418279A JP S5619250 A JPS5619250 A JP S5619250A
- Authority
- JP
- Japan
- Prior art keywords
- data
- clock
- timing
- received
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 238000005070 sampling Methods 0.000 abstract 1
- 230000001360 synchronised effect Effects 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
- G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
- Time-Division Multiplex Systems (AREA)
- Small-Scale Networks (AREA)
Abstract
PURPOSE:To minimize the number of cables and maximize the transfer capacity, by carrying out the transfer of the synchronous data by the 1st and 2nd clocks plus the sampling clock and by use of the data bus bar. CONSTITUTION:The 1st clock cl1 is a timing signal which is used when the rise is formed for the start request signal plus the read and write request signals each and the read and write data are set or received. And the 2nd clock cl2 is a timing signal which is used when the start timing of the frame is given. And in case the write data is transferred, the data sent via data bus bar 221 is received temporarily at received data register 311 and in the timing of clock cls and then stored in data buffer 304 in the peripheral unit. In this case, the head pulse of clock cl1 is used for starting, and the 2nd and 3rd pulses are used for transfer of the data each. And in case the read data is transferred, the data is set to the received data register in the timing of clock cls for the information processor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9418279A JPS5619250A (en) | 1979-07-26 | 1979-07-26 | Information transmitting system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9418279A JPS5619250A (en) | 1979-07-26 | 1979-07-26 | Information transmitting system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5619250A true JPS5619250A (en) | 1981-02-23 |
JPS6356736B2 JPS6356736B2 (en) | 1988-11-09 |
Family
ID=14103172
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9418279A Granted JPS5619250A (en) | 1979-07-26 | 1979-07-26 | Information transmitting system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5619250A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6110342A (en) * | 1984-06-26 | 1986-01-17 | Agency Of Ind Science & Technol | Computer network |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4912713A (en) * | 1972-04-03 | 1974-02-04 | ||
JPS52110506A (en) * | 1976-03-10 | 1977-09-16 | Chestel Inc | Communication switching system |
JPS5478601A (en) * | 1977-11-14 | 1979-06-22 | Vdo Schindling | Time sharing multiplex data transmitter |
-
1979
- 1979-07-26 JP JP9418279A patent/JPS5619250A/en active Granted
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4912713A (en) * | 1972-04-03 | 1974-02-04 | ||
JPS52110506A (en) * | 1976-03-10 | 1977-09-16 | Chestel Inc | Communication switching system |
JPS5478601A (en) * | 1977-11-14 | 1979-06-22 | Vdo Schindling | Time sharing multiplex data transmitter |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6110342A (en) * | 1984-06-26 | 1986-01-17 | Agency Of Ind Science & Technol | Computer network |
Also Published As
Publication number | Publication date |
---|---|
JPS6356736B2 (en) | 1988-11-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
YU271978A (en) | Clock system improvement at a data processing system | |
GB2009984B (en) | Data buffer memory | |
GB2009983A (en) | Data buffer memory | |
WO1996038793A3 (en) | Method and apparatus for adapting an asynchronous bus to a synchronous circuit | |
GB1394548A (en) | Data recirculator | |
GB2009980B (en) | Data buffer memory | |
JPS5619250A (en) | Information transmitting system | |
DE69131454D1 (en) | Data processor for pulse signal generation in response to an external clock signal | |
EP0056136A3 (en) | Flowmeter system with synchronous clock for generation of timing signals | |
JPS5533213A (en) | Information processing system | |
JPS53129540A (en) | Display system of word processor | |
JPS5230123A (en) | Time sharing using method of display memory | |
JPS6478362A (en) | One connection preparation of several data processors for central clock control multi-line system | |
SU1485259A1 (en) | Memory reference control unit | |
SU1405090A1 (en) | Buffer memory | |
JPS53148937A (en) | Data transfer system | |
FRANKEL et al. | Data buffer apparatus between subsystems which operate at differing or varying data rates[Patent] | |
JPS54158120A (en) | Signal phase conversion device | |
JPS57125425A (en) | System for information transmission | |
SU771658A1 (en) | Information input device | |
JPS53116041A (en) | System controller | |
JPS5779749A (en) | Packet transmission system | |
JPS54154214A (en) | Multi-character broadcast transmitter-receiver | |
JPS5454537A (en) | Data processing system | |
JPS5459043A (en) | Interface device |