[go: up one dir, main page]

JPS56149642A - Multiplier - Google Patents

Multiplier

Info

Publication number
JPS56149642A
JPS56149642A JP5257580A JP5257580A JPS56149642A JP S56149642 A JPS56149642 A JP S56149642A JP 5257580 A JP5257580 A JP 5257580A JP 5257580 A JP5257580 A JP 5257580A JP S56149642 A JPS56149642 A JP S56149642A
Authority
JP
Japan
Prior art keywords
register
multiplication
shifted
result
partial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5257580A
Other languages
Japanese (ja)
Inventor
Ryushi Hiroya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5257580A priority Critical patent/JPS56149642A/en
Publication of JPS56149642A publication Critical patent/JPS56149642A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)

Abstract

PURPOSE:To reduce the time required for a multiplication, by making use of an operation result of the partial multiplication that is stored in the ROM and calculating with the multipliers lumped with every plural digits. CONSTITUTION:The multiplicand and multiplier are stored in the MD register 1 and the MR register 2 respectively. Thus the lower two digits of MR register are added to the decoder 21 to be decoded. One of ROMs 25, 26 and 27 storing the partial integration is selected. The contents of the selected ROM is read with the multiplicand defined as an address and then supplied to the adder 4 to be added together with the contents of the partial multiplication register 5 received an operation previously. The result of this addition is shifted to the register 5, and the two bits of lower part are shifted out to the register 6. And the rest is fed back to the adder 5. This procedure is repeated to obtain a result of multiplication at the register 5 and the shifted-out register 6.
JP5257580A 1980-04-21 1980-04-21 Multiplier Pending JPS56149642A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5257580A JPS56149642A (en) 1980-04-21 1980-04-21 Multiplier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5257580A JPS56149642A (en) 1980-04-21 1980-04-21 Multiplier

Publications (1)

Publication Number Publication Date
JPS56149642A true JPS56149642A (en) 1981-11-19

Family

ID=12918599

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5257580A Pending JPS56149642A (en) 1980-04-21 1980-04-21 Multiplier

Country Status (1)

Country Link
JP (1) JPS56149642A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59180632A (en) * 1983-03-31 1984-10-13 Toshiba Corp Arithmetic unit
JPS6368048U (en) * 1987-09-30 1988-05-07

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4942182A (en) * 1972-04-27 1974-04-20
JPS5381030A (en) * 1976-12-27 1978-07-18 Takeda Riken Ind Co Ltd Multiplication table memory
JPS543441A (en) * 1977-06-10 1979-01-11 Hitachi Ltd High-speed arithmetic system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4942182A (en) * 1972-04-27 1974-04-20
JPS5381030A (en) * 1976-12-27 1978-07-18 Takeda Riken Ind Co Ltd Multiplication table memory
JPS543441A (en) * 1977-06-10 1979-01-11 Hitachi Ltd High-speed arithmetic system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59180632A (en) * 1983-03-31 1984-10-13 Toshiba Corp Arithmetic unit
JPS6368048U (en) * 1987-09-30 1988-05-07

Similar Documents

Publication Publication Date Title
JPS57141753A (en) Multiplication circuit
GB1336930A (en) Flow-through arithmetic apparatus
JPS55153052A (en) Digital multiplier
JPS56149642A (en) Multiplier
JPS54117646A (en) Computer
JPS57199044A (en) Multiplying device
WO1996038780A3 (en) Method for performing signed division
JPS5741738A (en) Digital multiplier
JPS5764864A (en) Digital arithmetic circuit
JPS52147287A (en) Process control equipment
JPS5668833A (en) Shift process system by multiplier
JPS5725039A (en) Dividing circuit
JPS5323150A (en) Multi-chamber tank
JPS5741737A (en) Dividing device
JPS55164941A (en) Multiplication circuit
JPS5642869A (en) Motion picture/still picture separator
JPS5624646A (en) Divider
JPS54159833A (en) Decimal multiplier
JPS643734A (en) Multiplication circuit
JPS5672739A (en) High-speed multiplying circuit
JPS6484333A (en) Divider
JPS54159832A (en) Adder and subtractor for numbers different in data length
JPS5611548A (en) Division unit
JPS6423333A (en) Division circuit
JPS5761322A (en) Digital filter