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JPS56148859A - Capacity element - Google Patents

Capacity element

Info

Publication number
JPS56148859A
JPS56148859A JP5251980A JP5251980A JPS56148859A JP S56148859 A JPS56148859 A JP S56148859A JP 5251980 A JP5251980 A JP 5251980A JP 5251980 A JP5251980 A JP 5251980A JP S56148859 A JPS56148859 A JP S56148859A
Authority
JP
Japan
Prior art keywords
region
forming
capacity
type impurity
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5251980A
Other languages
Japanese (ja)
Inventor
Toru Kuwabara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP5251980A priority Critical patent/JPS56148859A/en
Publication of JPS56148859A publication Critical patent/JPS56148859A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/62—Capacitors having potential barriers
    • H10D1/66—Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors

Landscapes

  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To manufacture a capacity element having less irregularity due to the variation in the wafer process parameter without input voltage dependency by doping impurity in high density on the surface layer of a semiconductor region. CONSTITUTION:In a silicon gate capacitor having a p<-> type impurity region 2 surrounded by a field oxide film 4 on an n type impurity substrate 1, a gate oxide film 5 forming an insulating film and a polycrystalline silicon layer 6 forming an electrode, a region (p<+> type region) 10 doped with a p type impurity having higher density than the region 2 is formed. The region 3 is connected to VDD as the high potential side of a power source, the region 2 thus becomes VDD of the potential, and a capacity is formed between the region 2 and a polycrystalline silicon layer 6 forming a signal line. Even if the applied voltage varies at this time, a depletion layer does not form by a p<+> type region 10, thereby eliminating the voltage dependency of the capacity.
JP5251980A 1980-04-18 1980-04-18 Capacity element Pending JPS56148859A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5251980A JPS56148859A (en) 1980-04-18 1980-04-18 Capacity element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5251980A JPS56148859A (en) 1980-04-18 1980-04-18 Capacity element

Publications (1)

Publication Number Publication Date
JPS56148859A true JPS56148859A (en) 1981-11-18

Family

ID=12916981

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5251980A Pending JPS56148859A (en) 1980-04-18 1980-04-18 Capacity element

Country Status (1)

Country Link
JP (1) JPS56148859A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0388564A2 (en) * 1988-02-11 1990-09-26 STMicroelectronics, Inc. Method for forming a non-planar structure on the surface of a semiconductor substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0388564A2 (en) * 1988-02-11 1990-09-26 STMicroelectronics, Inc. Method for forming a non-planar structure on the surface of a semiconductor substrate

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