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JPS56124255A - Mos type integrated circuit - Google Patents

Mos type integrated circuit

Info

Publication number
JPS56124255A
JPS56124255A JP2641580A JP2641580A JPS56124255A JP S56124255 A JPS56124255 A JP S56124255A JP 2641580 A JP2641580 A JP 2641580A JP 2641580 A JP2641580 A JP 2641580A JP S56124255 A JPS56124255 A JP S56124255A
Authority
JP
Japan
Prior art keywords
vdd
charge holding
voltage
charging
vth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2641580A
Other languages
Japanese (ja)
Other versions
JPS6216554B2 (en
Inventor
Hiroyuki Kinoshita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP2641580A priority Critical patent/JPS56124255A/en
Priority to US06/237,699 priority patent/US4433257A/en
Priority to GB8105971A priority patent/GB2072419B/en
Priority to DE3107902A priority patent/DE3107902C2/en
Publication of JPS56124255A publication Critical patent/JPS56124255A/en
Publication of JPS6216554B2 publication Critical patent/JPS6216554B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To improve charge holding characteristic while maintaining satisfactory charging characteristic, without impressing high voltage directly onto an FET drain for charging of a peripheral circuit, by making and supplying a voltage lower than the above voltage at a place distant from a charge holding section in a chip. CONSTITUTION:An enhancement type FET T0, prepared by connecting a drain and a gate to a high voltage power source VDD, is newly installed at a place distant from a charge holding section, and a source voltage V0 is supplied to drains of charging FET T1-Tm of all the decoders D. gm of T0 is to be larger than those of T1-Tm. In this state, ''I'' voltage of the decoder is charged up to VDD-Vth, the charging characteristic remain almost same as the conventional, and VDD-Vth are impressed on the drains of T1-Tm and VDD is impressed on the gate and operating in a tripolar tube region to control occurrence of minor carrier, and therefore, charge holding characteristic of a memory cell is extremely improved. In case when T1-Tm are controlled by clock signal, if V0 is kept much lower than VDD-Vth in normal condition, it is possible to minimize occurrence minor carrier at the time of clock phi.
JP2641580A 1980-03-03 1980-03-03 Mos type integrated circuit Granted JPS56124255A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2641580A JPS56124255A (en) 1980-03-03 1980-03-03 Mos type integrated circuit
US06/237,699 US4433257A (en) 1980-03-03 1981-02-24 Voltage supply for operating a plurality of changing transistors in a manner which reduces minority carrier disruption of adjacent memory cells
GB8105971A GB2072419B (en) 1980-03-03 1981-02-25 Mos integrated circuit device
DE3107902A DE3107902C2 (en) 1980-03-03 1981-03-02 Integrated MOS circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2641580A JPS56124255A (en) 1980-03-03 1980-03-03 Mos type integrated circuit

Publications (2)

Publication Number Publication Date
JPS56124255A true JPS56124255A (en) 1981-09-29
JPS6216554B2 JPS6216554B2 (en) 1987-04-13

Family

ID=12192905

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2641580A Granted JPS56124255A (en) 1980-03-03 1980-03-03 Mos type integrated circuit

Country Status (1)

Country Link
JP (1) JPS56124255A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5745267A (en) * 1980-09-01 1982-03-15 Nec Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5745267A (en) * 1980-09-01 1982-03-15 Nec Corp Semiconductor device
JPS6335106B2 (en) * 1980-09-01 1988-07-13 Nippon Electric Co

Also Published As

Publication number Publication date
JPS6216554B2 (en) 1987-04-13

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