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JPS54158141A - Drift compensation circuit for analog memory - Google Patents

Drift compensation circuit for analog memory

Info

Publication number
JPS54158141A
JPS54158141A JP6740078A JP6740078A JPS54158141A JP S54158141 A JPS54158141 A JP S54158141A JP 6740078 A JP6740078 A JP 6740078A JP 6740078 A JP6740078 A JP 6740078A JP S54158141 A JPS54158141 A JP S54158141A
Authority
JP
Japan
Prior art keywords
mosfet
reading
analog quantity
voltage
compensation circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6740078A
Other languages
Japanese (ja)
Other versions
JPS6044754B2 (en
Inventor
Yoshinosuke Nagata
Kazuyoshi Tsukamoto
Takao Nakatsuka
Yasuki Rai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP53067400A priority Critical patent/JPS6044754B2/en
Publication of JPS54158141A publication Critical patent/JPS54158141A/en
Publication of JPS6044754B2 publication Critical patent/JPS6044754B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Non-Volatile Memory (AREA)
  • Read Only Memory (AREA)

Abstract

PURPOSE: To ensure the temperature compensation for the analog quantity at the reading time by applying the gate voltage of the floating gate type MOSFET which is to be an analog memory via the MOSFET featuring the same characteristics at the floating gate type MOSFET.
CONSTITUTION: The accumulated analog quantity varies by the reading gate voltage, and accordingly the reading voltage is varied in accordance with the temperature drift. This reading voltage is obtained from the output of MOSFET(T) which is cascade-connected to memory FET. In other words, both the gate voltage applied to MOSFET(T) and the characteristics of the drain current function in the direction where the temperature drift of the memory FET is offset. As a result, the temperature is compensated at the reading time of the analog quantity.
COPYRIGHT: (C)1979,JPO&Japio
JP53067400A 1978-06-02 1978-06-02 Analog memory drift compensation circuit Expired JPS6044754B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53067400A JPS6044754B2 (en) 1978-06-02 1978-06-02 Analog memory drift compensation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53067400A JPS6044754B2 (en) 1978-06-02 1978-06-02 Analog memory drift compensation circuit

Publications (2)

Publication Number Publication Date
JPS54158141A true JPS54158141A (en) 1979-12-13
JPS6044754B2 JPS6044754B2 (en) 1985-10-05

Family

ID=13343859

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53067400A Expired JPS6044754B2 (en) 1978-06-02 1978-06-02 Analog memory drift compensation circuit

Country Status (1)

Country Link
JP (1) JPS6044754B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02193398A (en) * 1989-01-20 1990-07-31 Toshiba Corp Method and apparatus for applying program voltage to nonvolatile semiconductor memory
US5043940A (en) * 1988-06-08 1991-08-27 Eliyahou Harari Flash EEPROM memory systems having multistate storage cells
US5268870A (en) * 1988-06-08 1993-12-07 Eliyahou Harari Flash EEPROM system and intelligent programming and erasing methods therefor
US5293560A (en) * 1988-06-08 1994-03-08 Eliyahou Harari Multi-state flash EEPROM system using incremental programing and erasing methods
US5963480A (en) * 1988-06-08 1999-10-05 Harari; Eliyahou Highly compact EPROM and flash EEPROM devices
US8040727B1 (en) 1989-04-13 2011-10-18 Sandisk Corporation Flash EEprom system with overhead data stored in user data sectors

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5568439A (en) * 1988-06-08 1996-10-22 Harari; Eliyahou Flash EEPROM system which maintains individual memory block cycle counts
US5835415A (en) * 1988-06-08 1998-11-10 Harari; Eliyahou Flash EEPROM memory systems and methods of using them
US5268870A (en) * 1988-06-08 1993-12-07 Eliyahou Harari Flash EEPROM system and intelligent programming and erasing methods therefor
US5293560A (en) * 1988-06-08 1994-03-08 Eliyahou Harari Multi-state flash EEPROM system using incremental programing and erasing methods
US5434825A (en) * 1988-06-08 1995-07-18 Harari; Eliyahou Flash EEPROM system cell array with more than two storage states per memory cell
US5544118A (en) * 1988-06-08 1996-08-06 Harari; Eliyahou Flash EEPROM system cell array with defect management including an error correction scheme
US5043940A (en) * 1988-06-08 1991-08-27 Eliyahou Harari Flash EEPROM memory systems having multistate storage cells
US5642312A (en) * 1988-06-08 1997-06-24 Harari; Eliyahou Flash EEPROM system cell array with more than two storage states per memory cell
US5963480A (en) * 1988-06-08 1999-10-05 Harari; Eliyahou Highly compact EPROM and flash EEPROM devices
US5712819A (en) * 1988-06-08 1998-01-27 Harari; Eliyahou Flash EEPROM system with storage of sector characteristic information within the sector
US5583812A (en) * 1988-06-08 1996-12-10 Harari; Eliyahou Flash EEPROM system cell array with more than two storage states per memory cell
US5862081A (en) * 1988-06-08 1999-01-19 Harari; Eliyahou Multi-state flash EEPROM system with defect management including an error correction scheme
US5909390A (en) * 1988-06-08 1999-06-01 Harari; Eliyahou Techniques of programming and erasing an array of multi-state flash EEPROM cells including comparing the states of the cells to desired values
JPH02193398A (en) * 1989-01-20 1990-07-31 Toshiba Corp Method and apparatus for applying program voltage to nonvolatile semiconductor memory
US8040727B1 (en) 1989-04-13 2011-10-18 Sandisk Corporation Flash EEprom system with overhead data stored in user data sectors

Also Published As

Publication number Publication date
JPS6044754B2 (en) 1985-10-05

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