[go: up one dir, main page]

JPS56123026A - Input and output controlling system - Google Patents

Input and output controlling system

Info

Publication number
JPS56123026A
JPS56123026A JP2748280A JP2748280A JPS56123026A JP S56123026 A JPS56123026 A JP S56123026A JP 2748280 A JP2748280 A JP 2748280A JP 2748280 A JP2748280 A JP 2748280A JP S56123026 A JPS56123026 A JP S56123026A
Authority
JP
Japan
Prior art keywords
log
channel
status information
cpu
ioc
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2748280A
Other languages
Japanese (ja)
Inventor
Hidehiko Serikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2748280A priority Critical patent/JPS56123026A/en
Publication of JPS56123026A publication Critical patent/JPS56123026A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0745—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in an input/output transactions management context
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To gather status information without lowering the efficiency of the whole of the system, by reading status information of I/O devices independently of instructions of the host device by channels themselves when channels detect errors. CONSTITUTION:When an error is detected on channel CH during data transfer from CPU to channel CH, channel CH stops the data transfer sequence and preserve status information of channel CH in log-out data buffer 3 and transmits the selective reset signal to the I/O device side and causes the ICC (interface control check) interrupt to CPU. I/O control device IOC which received the selective reset signal preserves its own status information in log-out buffer 5. The channel writes log-out data from IOC and its own log data into the memory of CPU after transfer of log- out data from IOC.
JP2748280A 1980-03-04 1980-03-04 Input and output controlling system Pending JPS56123026A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2748280A JPS56123026A (en) 1980-03-04 1980-03-04 Input and output controlling system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2748280A JPS56123026A (en) 1980-03-04 1980-03-04 Input and output controlling system

Publications (1)

Publication Number Publication Date
JPS56123026A true JPS56123026A (en) 1981-09-26

Family

ID=12222340

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2748280A Pending JPS56123026A (en) 1980-03-04 1980-03-04 Input and output controlling system

Country Status (1)

Country Link
JP (1) JPS56123026A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61118846A (en) * 1984-11-15 1986-06-06 Fujitsu Ltd Fault information collection system of subsystem
JPH0342749A (en) * 1989-07-11 1991-02-22 Fujitsu Ltd Input/output controller

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61118846A (en) * 1984-11-15 1986-06-06 Fujitsu Ltd Fault information collection system of subsystem
JPH0342749A (en) * 1989-07-11 1991-02-22 Fujitsu Ltd Input/output controller

Similar Documents

Publication Publication Date Title
DE3854516D1 (en) Input / output interface of a fault-tolerant computer system.
JPS53125738A (en) Device for reporting status
EP0049159A3 (en) Bus interface in communication controller
JPS56123026A (en) Input and output controlling system
JPS57164329A (en) Display controlling system
JPS5694596A (en) Memory control system
JPS5534756A (en) Double recording system of magnetic disc device
JPS56149651A (en) Checking system of parity detecting function
SE7907217L (en) COMPUTER IN / OUTDOOR CONTROL DEVICE
JPS56156981A (en) Bubble memory device
JPS5667426A (en) Processing system for failed data
JPS53122340A (en) Check system for read-in data
JPS5755446A (en) Check system for digital transfer data
JPS5667425A (en) Processing system for failed data
JPS56132645A (en) Check system of input data selection signal for register
JPS54146532A (en) Memory device
JPS5452938A (en) Channel control system
JPS57109020A (en) Bus interface control system
JPS56153592A (en) Output memory device
JPS57109021A (en) Input and output control system
JPS5714925A (en) Initializing system
JPS5714238A (en) Connection device for synchronous circuit
JPS5587254A (en) Parity check system for two-way bus
JPS5451347A (en) Fault detection system of data processor
JPS5528107A (en) Trnsmission and reception method of signal