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JPS56115572A - Field effect transistor - Google Patents

Field effect transistor

Info

Publication number
JPS56115572A
JPS56115572A JP1875280A JP1875280A JPS56115572A JP S56115572 A JPS56115572 A JP S56115572A JP 1875280 A JP1875280 A JP 1875280A JP 1875280 A JP1875280 A JP 1875280A JP S56115572 A JPS56115572 A JP S56115572A
Authority
JP
Japan
Prior art keywords
region
type
substrate
drain
field effect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1875280A
Other languages
Japanese (ja)
Other versions
JPH0116027B2 (en
Inventor
Sukemitsu Takena
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1875280A priority Critical patent/JPS56115572A/en
Publication of JPS56115572A publication Critical patent/JPS56115572A/en
Publication of JPH0116027B2 publication Critical patent/JPH0116027B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/343—Gate regions of field-effect devices having PN junction gates

Landscapes

  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To increase the withstand voltage of the field effect transistor by forming the other conductivity type first region having a predetermined depth at an interval in one conductivity type semiconductor substrate becoming a drain and forming a gate between first regions and a source in the junction between the first region and the substrate. CONSTITUTION:With high density N<+> type substrate as a drain a P type region 7 is formed in a predetermined depth from the surface to have a part confronting at a predetermined interval on the upper surface of the N<-> type region 9 formed on the substrate 10. A P<+> type region 8 is formed at the part confronting the region 7 on the upper surface of the region 9 as the first gate region. A high density N<+> type region 6 is so formed as a source across the P-N junction between the regions 7 and 9. A P<+> type region 7' is formed at the part confronting the region 7 as the second gate region. The region 7 is formed sufficiently deeply, thereby increasing the withstand voltage between the drain and the source.
JP1875280A 1980-02-18 1980-02-18 Field effect transistor Granted JPS56115572A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1875280A JPS56115572A (en) 1980-02-18 1980-02-18 Field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1875280A JPS56115572A (en) 1980-02-18 1980-02-18 Field effect transistor

Publications (2)

Publication Number Publication Date
JPS56115572A true JPS56115572A (en) 1981-09-10
JPH0116027B2 JPH0116027B2 (en) 1989-03-22

Family

ID=11980377

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1875280A Granted JPS56115572A (en) 1980-02-18 1980-02-18 Field effect transistor

Country Status (1)

Country Link
JP (1) JPS56115572A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009540771A (en) * 2006-06-13 2009-11-19 ディーエスエム ソリューションズ，インコーポレイテッド Circuit configuration with 4-terminal JFET device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5026484A (en) * 1973-07-06 1975-03-19

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5026484A (en) * 1973-07-06 1975-03-19

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009540771A (en) * 2006-06-13 2009-11-19 ディーエスエム ソリューションズ，インコーポレイテッド Circuit configuration with 4-terminal JFET device

Also Published As

Publication number Publication date
JPH0116027B2 (en) 1989-03-22

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