JPS56107634A - Decoder - Google Patents
DecoderInfo
- Publication number
- JPS56107634A JPS56107634A JP1025580A JP1025580A JPS56107634A JP S56107634 A JPS56107634 A JP S56107634A JP 1025580 A JP1025580 A JP 1025580A JP 1025580 A JP1025580 A JP 1025580A JP S56107634 A JPS56107634 A JP S56107634A
- Authority
- JP
- Japan
- Prior art keywords
- dec3
- information
- output
- unit
- borrow
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
PURPOSE:Not to output the erroneous information transiently, by making an output of each input decoder ineffective for a prescribed time, when carry or borrow has been detected by variation of the input information. CONSTITUTION:The inputs A1, B1, C1, D1 which are the bit information of the binary code corresponding to the digit of 1 of decimal number are converted to the decimal numbers by the unit decoder DEC3. In the same way, the inputs A10, B10, C10, D10 which are the bit information of the binary code corresponding to the digit of 10 of decimal number are converted to the decimal numbers by the unit decoder DEC4. And, in case when the binary code information by which ''1'' is increased or decreased in order is input, when carry or borrow has occurred, both the outputs of the unit decoders DEC3, 4 are varied. Accordingly, when there is a difference of the operation time in both the unit decoders DEC3, 4, the erroneous information is output, therefore the carry or the borrow is detected by the digit change detection circuit ED, and by this output EB, the outputs of the respective unit decoders DEC3, 4 are made ineffective for a prescribed time.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1025580A JPS56107634A (en) | 1980-01-31 | 1980-01-31 | Decoder |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1025580A JPS56107634A (en) | 1980-01-31 | 1980-01-31 | Decoder |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56107634A true JPS56107634A (en) | 1981-08-26 |
Family
ID=11745203
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1025580A Pending JPS56107634A (en) | 1980-01-31 | 1980-01-31 | Decoder |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56107634A (en) |
-
1980
- 1980-01-31 JP JP1025580A patent/JPS56107634A/en active Pending
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