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JPS56105672A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS56105672A
JPS56105672A JP853180A JP853180A JPS56105672A JP S56105672 A JPS56105672 A JP S56105672A JP 853180 A JP853180 A JP 853180A JP 853180 A JP853180 A JP 853180A JP S56105672 A JPS56105672 A JP S56105672A
Authority
JP
Japan
Prior art keywords
layer
psg
segment
melting point
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP853180A
Other languages
Japanese (ja)
Inventor
Isamu Miyagi
Shigehisa Wakamatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP853180A priority Critical patent/JPS56105672A/en
Publication of JPS56105672A publication Critical patent/JPS56105672A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To obtain a desired pattern by self-metching by a method wherein a layer of a material I and a layer of material II lower than the material I at melting point are layer-built to be formed on a semiconductor suhstrate, the material II being the prescribed pattern and the material I is selectively corroded with the pattern as a mask and after then, the material I is covered with the material II heated as high as the melting point or over. CONSTITUTION:An Si3N4 film 9 to be made the material I and PSG layer 10 of the material II decreased in the melting point by being contained with phosphorus of 5mol% or more are layer-built to be grown on an N type Si epitaxial layer 8. Then, the layer 10 is applied a photoetching to be made a PSG segment 11 of the desired pattern and the film 9 at the part exposed is etching-removed by hot phosphoric acid. Thereafter, the substrate 8 inlcuding the remained PSG segment 11 and an Si3N4 layer 12 under the segment 11 is applied a heat treatment at 1,050 deg.C in the atmosphere of boric gas to cause the PSG segment 11 of 980 deg.C at the melting point to be fused and to surround the film 12. At the same time, a BSG layer 13 liquified at about over 400 deg.C is spread all over the surface and the boron in the PSG is diffused to cause a P type region 14 to be produced in the substrate 8 around the film 12.
JP853180A 1980-01-28 1980-01-28 Manufacture of semiconductor device Pending JPS56105672A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP853180A JPS56105672A (en) 1980-01-28 1980-01-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP853180A JPS56105672A (en) 1980-01-28 1980-01-28 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS56105672A true JPS56105672A (en) 1981-08-22

Family

ID=11695724

Family Applications (1)

Application Number Title Priority Date Filing Date
JP853180A Pending JPS56105672A (en) 1980-01-28 1980-01-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS56105672A (en)

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