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JPS56103748A - Memory system - Google Patents

Memory system

Info

Publication number
JPS56103748A
JPS56103748A JP643980A JP643980A JPS56103748A JP S56103748 A JPS56103748 A JP S56103748A JP 643980 A JP643980 A JP 643980A JP 643980 A JP643980 A JP 643980A JP S56103748 A JPS56103748 A JP S56103748A
Authority
JP
Japan
Prior art keywords
memory
modules
address
line
assigning
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP643980A
Other languages
Japanese (ja)
Inventor
Kazuyuki Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP643980A priority Critical patent/JPS56103748A/en
Publication of JPS56103748A publication Critical patent/JPS56103748A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To give the degree of freedom to the combination of various types of memory modules, by assigning the priority to the memory access to each memory module, allowing to permit the duplication of memory area partly. CONSTITUTION:A memory system 10 is constituted by connecting each of memory modules 111-11n by means of an address line 19 and a memory start signal line 20. The memory modules 111-11n are provided with address decoders 121-12n and memory sections 181-18n. Further, the line 20 is provided with a logic gate circuit which discriminates the condition of the first and second enable signals E11-E1n, E21-E2n assigning the priority. Moreover, the address of itself is discriminated with the decoders 121-12n and a logical gate circuit discriminates the signals E11-E1n, E21-E2n, to output the logic 1, then the memory sections 181-18n can be accessed, allowing to give the degree of freedom to the combination of various types of modules 111-11n.
JP643980A 1980-01-23 1980-01-23 Memory system Pending JPS56103748A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP643980A JPS56103748A (en) 1980-01-23 1980-01-23 Memory system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP643980A JPS56103748A (en) 1980-01-23 1980-01-23 Memory system

Publications (1)

Publication Number Publication Date
JPS56103748A true JPS56103748A (en) 1981-08-19

Family

ID=11638423

Family Applications (1)

Application Number Title Priority Date Filing Date
JP643980A Pending JPS56103748A (en) 1980-01-23 1980-01-23 Memory system

Country Status (1)

Country Link
JP (1) JPS56103748A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63135442U (en) * 1987-02-25 1988-09-06
JPH0744455A (en) * 1993-07-26 1995-02-14 Nec Corp Address decoder

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63135442U (en) * 1987-02-25 1988-09-06
JPH0744455A (en) * 1993-07-26 1995-02-14 Nec Corp Address decoder

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