JPS56102116A - Pseudo-noise signal generating circuit - Google Patents
Pseudo-noise signal generating circuitInfo
- Publication number
- JPS56102116A JPS56102116A JP436280A JP436280A JPS56102116A JP S56102116 A JPS56102116 A JP S56102116A JP 436280 A JP436280 A JP 436280A JP 436280 A JP436280 A JP 436280A JP S56102116 A JPS56102116 A JP S56102116A
- Authority
- JP
- Japan
- Prior art keywords
- shift
- pseudo
- phase shift
- counter
- noise signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/84—Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
PURPOSE:To make it possible to optionally set shift amount of pseudo-noise signals and shift at every integer of its series period, by sending synchronous pulses of the counter to the on/off control circuit through external phase controlling signals, and by performing the off control and phase shift on the clock signal. CONSTITUTION:The output of each stage of multistage shift register 2 is added to pattern detector 10. At this circuit 10 a synchronous pulse is generated at every one period of the pseudo-noise signal series, and a constant phase shift is received at fixed phase shift circuit 12 and then sent to 1/N counter 11. At counter 11 synchronous pulses of N periods are sent to on/off control circuit 8 through external phase controlling signal 9, and the off control is performed on clock signal 1 and phase shift is executed on noise signals. By this, the location from which phase shift of pseudo-noise signal is commenced, shift amount, the execution of shift at every integer of its series period can be set optionally.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP436280A JPS56102116A (en) | 1980-01-18 | 1980-01-18 | Pseudo-noise signal generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP436280A JPS56102116A (en) | 1980-01-18 | 1980-01-18 | Pseudo-noise signal generating circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56102116A true JPS56102116A (en) | 1981-08-15 |
| JPS6322090B2 JPS6322090B2 (en) | 1988-05-10 |
Family
ID=11582258
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP436280A Granted JPS56102116A (en) | 1980-01-18 | 1980-01-18 | Pseudo-noise signal generating circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56102116A (en) |
-
1980
- 1980-01-18 JP JP436280A patent/JPS56102116A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6322090B2 (en) | 1988-05-10 |
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