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JPS5597627A - On-line terminal control unit - Google Patents

On-line terminal control unit

Info

Publication number
JPS5597627A
JPS5597627A JP468679A JP468679A JPS5597627A JP S5597627 A JPS5597627 A JP S5597627A JP 468679 A JP468679 A JP 468679A JP 468679 A JP468679 A JP 468679A JP S5597627 A JPS5597627 A JP S5597627A
Authority
JP
Japan
Prior art keywords
data
processor
terminal unit
request signal
central processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP468679A
Other languages
Japanese (ja)
Inventor
Shinji Tsunoda
Ikuo Kondo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP468679A priority Critical patent/JPS5597627A/en
Publication of JPS5597627A publication Critical patent/JPS5597627A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)
  • Computer And Data Communications (AREA)

Abstract

PURPOSE: To realize the transfer of information from the central processor with no effect given by the function of the output terminal unit, by incorporating the buffer unit incorporating the data input/output control function between the central processor and the output terminal unit.
CONSTITUTION: In case the control of the terminal unit is required at central processor (CPU) 1, CPU1 supplies the request signal to control arithmetic processor 4 via input mechanism 3. Processor 4 has checking to decide whether the data reception is possible or not to the request, and then transmits the permission signal to wait for the data if the data reception is possible. The CPU transfers the data by one block via the permission signal, and then drops the request signal when the transfer ends. Processor 4 receives the data while giving checking to the request signal and then stores the data into data memory 6. After this processor 4 extracts the data out of memory 6 and then sends it to terminal unit 2 via output mechanism 7 and in the form corresponding to the terminal.
COPYRIGHT: (C)1980,JPO&Japio
JP468679A 1979-01-18 1979-01-18 On-line terminal control unit Pending JPS5597627A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP468679A JPS5597627A (en) 1979-01-18 1979-01-18 On-line terminal control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP468679A JPS5597627A (en) 1979-01-18 1979-01-18 On-line terminal control unit

Publications (1)

Publication Number Publication Date
JPS5597627A true JPS5597627A (en) 1980-07-25

Family

ID=11590768

Family Applications (1)

Application Number Title Priority Date Filing Date
JP468679A Pending JPS5597627A (en) 1979-01-18 1979-01-18 On-line terminal control unit

Country Status (1)

Country Link
JP (1) JPS5597627A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62194550A (en) * 1986-02-20 1987-08-27 Nec Corp Emulator for slave processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62194550A (en) * 1986-02-20 1987-08-27 Nec Corp Emulator for slave processor

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