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JPS5591827A - Production of semiconductor device - Google Patents

Production of semiconductor device

Info

Publication number
JPS5591827A
JPS5591827A JP16571378A JP16571378A JPS5591827A JP S5591827 A JPS5591827 A JP S5591827A JP 16571378 A JP16571378 A JP 16571378A JP 16571378 A JP16571378 A JP 16571378A JP S5591827 A JPS5591827 A JP S5591827A
Authority
JP
Japan
Prior art keywords
opening
amorphous silicon
resist
gate
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16571378A
Other languages
Japanese (ja)
Other versions
JPS5832502B2 (en
Inventor
Shigero Kuninobu
Atsushi Ueno
Takeshi Ishihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP16571378A priority Critical patent/JPS5832502B2/en
Publication of JPS5591827A publication Critical patent/JPS5591827A/en
Publication of JPS5832502B2 publication Critical patent/JPS5832502B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Weting (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: To realize formation of a shallow diffusion layer of high density with high rapidity, by executing contact of MOS transistor of small occupancy area in a self- aligning manner and without high temperature heat-treatment.
CONSTITUTION: A field oxide film 12, a gate oxide film 13, an amorphous silicon gate 14 and an amorphous silicon wiring layers 15 and 15' are formed on a p-type silicon substrate 11, and a drain region 16' are formed by the ion injection method. Secondly, an SiO2 film 17 is formed, and then, a negative type photoresist layer 18 and a positive type photoresist layer 19 are also formed. By providing an opening 20 on the resist layer 19 by conducting exposure and development, the resist 18 exposed at the opening is etched. At this time, the thick resist 18' is not compeletely removed even if the opening 20 of the gate section deviates a little, and therefore, it is possible to provide the opening on the amorphous silicon 14 while aligning the position by itself.
COPYRIGHT: (C)1980,JPO&Japio
JP16571378A 1978-12-29 1978-12-29 Manufacturing method of semiconductor device Expired JPS5832502B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16571378A JPS5832502B2 (en) 1978-12-29 1978-12-29 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16571378A JPS5832502B2 (en) 1978-12-29 1978-12-29 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5591827A true JPS5591827A (en) 1980-07-11
JPS5832502B2 JPS5832502B2 (en) 1983-07-13

Family

ID=15817638

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16571378A Expired JPS5832502B2 (en) 1978-12-29 1978-12-29 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5832502B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61104626A (en) * 1984-10-29 1986-05-22 Nippon Telegr & Teleph Corp <Ntt> Manufacture of semiconductor device
US5879997A (en) * 1991-05-30 1999-03-09 Lucent Technologies Inc. Method for forming self aligned polysilicon contact
US6350674B1 (en) * 1999-04-05 2002-02-26 Seiko Epson Corporation Manufacturing method for semiconductor device having a multilayer interconnect
US6376367B1 (en) 1999-03-12 2002-04-23 Seiko Epson Corporation Method for manufacturing multilayer interconnects by forming a trench with an underlying through-hole in a low dielectric constant insulator layer

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61104626A (en) * 1984-10-29 1986-05-22 Nippon Telegr & Teleph Corp <Ntt> Manufacture of semiconductor device
US5879997A (en) * 1991-05-30 1999-03-09 Lucent Technologies Inc. Method for forming self aligned polysilicon contact
US6376367B1 (en) 1999-03-12 2002-04-23 Seiko Epson Corporation Method for manufacturing multilayer interconnects by forming a trench with an underlying through-hole in a low dielectric constant insulator layer
US6350674B1 (en) * 1999-04-05 2002-02-26 Seiko Epson Corporation Manufacturing method for semiconductor device having a multilayer interconnect

Also Published As

Publication number Publication date
JPS5832502B2 (en) 1983-07-13

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