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JPS5591044A - Microprogram control system - Google Patents

Microprogram control system

Info

Publication number
JPS5591044A
JPS5591044A JP16497478A JP16497478A JPS5591044A JP S5591044 A JPS5591044 A JP S5591044A JP 16497478 A JP16497478 A JP 16497478A JP 16497478 A JP16497478 A JP 16497478A JP S5591044 A JPS5591044 A JP S5591044A
Authority
JP
Japan
Prior art keywords
address
fault
secure
jumping
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16497478A
Other languages
Japanese (ja)
Inventor
Ryushi Hiroya
Tsugio Umemiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16497478A priority Critical patent/JPS5591044A/en
Publication of JPS5591044A publication Critical patent/JPS5591044A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To realize execution of the normal operation when the specified same address has some fault in case the jumping microorder is stored in the above mentioned address to secure the dynamic stop state for the microprogram control system.
CONSTITUTION: Address n of the order which causes the dynamic stop state to control memory CM at the power make time is sent via address line A, and thus the contents turn to the order jumping to address n of its own to secure the idle state at address n. And in case the fault such as the parity error or the like occurs to the contents read out of address n, the fault is detected at fault detection circuit EC to deliver fault information E. At the same time, information En showing the fault occurrence is sent to sequence control unit SC to carry out the fault processing. After this, unit SC sends the address m to control memory CM in the form of the address information. The order jumping to address n is stored in address m, and address m is sent to memory CM via the conversion circuit to secure practically the dynamic stop state at address m.
COPYRIGHT: (C)1980,JPO&Japio
JP16497478A 1978-12-28 1978-12-28 Microprogram control system Pending JPS5591044A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16497478A JPS5591044A (en) 1978-12-28 1978-12-28 Microprogram control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16497478A JPS5591044A (en) 1978-12-28 1978-12-28 Microprogram control system

Publications (1)

Publication Number Publication Date
JPS5591044A true JPS5591044A (en) 1980-07-10

Family

ID=15803416

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16497478A Pending JPS5591044A (en) 1978-12-28 1978-12-28 Microprogram control system

Country Status (1)

Country Link
JP (1) JPS5591044A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5760444A (en) * 1980-09-30 1982-04-12 Fujitsu Ltd Microprogram control system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5760444A (en) * 1980-09-30 1982-04-12 Fujitsu Ltd Microprogram control system

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