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JPS5583263A - Mos semiconductor device - Google Patents

Mos semiconductor device

Info

Publication number
JPS5583263A
JPS5583263A JP15834778A JP15834778A JPS5583263A JP S5583263 A JPS5583263 A JP S5583263A JP 15834778 A JP15834778 A JP 15834778A JP 15834778 A JP15834778 A JP 15834778A JP S5583263 A JPS5583263 A JP S5583263A
Authority
JP
Japan
Prior art keywords
drain regions
source
channel
layer
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15834778A
Other languages
Japanese (ja)
Inventor
Haruhisa Mori
Nobuo Sasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15834778A priority Critical patent/JPS5583263A/en
Publication of JPS5583263A publication Critical patent/JPS5583263A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113Isolations within a component, i.e. internal isolations
    • H10D62/115Dielectric isolations, e.g. air gaps
    • H10D62/116Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions

Abstract

PURPOSE:To accelerate the operating speed of a transistor by burying an oxide layer in each of the bottoms of source and drain regions when diffusing the source and drain regions at both sides of a channel region. CONSTITUTION:A gate insulating film 10 buried internally with a gate electrode 10' is formed on a semiconductor substrate provided with a thick field oxide film 5 on the periphery thereof. Then, with the film 10 as a mask oxygen ion is implanted into the substrates at both sides of the mask while controlling the acceleration voltage to thereby produce maximum oxygen density region at predetermined depth, the substrate is then annealed to thereby form oxide layers 17 and 18. Then, shallow source and drain regions 13 and 14 are formed thereon by ion implantation or diffusion, and electrodes 13' and 14' are mounted thereat. Thus, the extension of a depletion layer from the channel layer 16 to the channel region 16 can be reduce to the degree to be ignored to thus become a short channel, and the dielectric constant of the oxide layer is lower than the substrate to thereby improve the operating speed of the transistor.
JP15834778A 1978-12-19 1978-12-19 Mos semiconductor device Pending JPS5583263A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15834778A JPS5583263A (en) 1978-12-19 1978-12-19 Mos semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15834778A JPS5583263A (en) 1978-12-19 1978-12-19 Mos semiconductor device

Publications (1)

Publication Number Publication Date
JPS5583263A true JPS5583263A (en) 1980-06-23

Family

ID=15669651

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15834778A Pending JPS5583263A (en) 1978-12-19 1978-12-19 Mos semiconductor device

Country Status (1)

Country Link
JP (1) JPS5583263A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1985000694A1 (en) * 1983-07-25 1985-02-14 American Telephone & Telegraph Company Shallow-junction semiconductor devices
US4683637A (en) * 1986-02-07 1987-08-04 Motorola, Inc. Forming depthwise isolation by selective oxygen/nitrogen deep implant and reaction annealing
JPH0278274A (en) * 1988-09-13 1990-03-19 Nec Corp Insulated gate field effect transistor
JPH0897231A (en) * 1994-09-28 1996-04-12 Nec Corp Method for manufacturing semiconductor device
KR100489586B1 (en) * 1997-12-30 2005-09-06 주식회사 하이닉스반도체 Method of forming junction part of semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1985000694A1 (en) * 1983-07-25 1985-02-14 American Telephone & Telegraph Company Shallow-junction semiconductor devices
US4683637A (en) * 1986-02-07 1987-08-04 Motorola, Inc. Forming depthwise isolation by selective oxygen/nitrogen deep implant and reaction annealing
WO1987004860A1 (en) * 1986-02-07 1987-08-13 Motorola, Inc. Partially dielectrically isolated semiconductor devices
JPH0278274A (en) * 1988-09-13 1990-03-19 Nec Corp Insulated gate field effect transistor
JPH0897231A (en) * 1994-09-28 1996-04-12 Nec Corp Method for manufacturing semiconductor device
KR100489586B1 (en) * 1997-12-30 2005-09-06 주식회사 하이닉스반도체 Method of forming junction part of semiconductor device

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