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JPS5557963A - Information processor - Google Patents

Information processor

Info

Publication number
JPS5557963A
JPS5557963A JP12998178A JP12998178A JPS5557963A JP S5557963 A JPS5557963 A JP S5557963A JP 12998178 A JP12998178 A JP 12998178A JP 12998178 A JP12998178 A JP 12998178A JP S5557963 A JPS5557963 A JP S5557963A
Authority
JP
Japan
Prior art keywords
register
control memory
microinstruction
display
display operation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12998178A
Other languages
Japanese (ja)
Other versions
JPS6213698B2 (en
Inventor
Masatoshi Tominaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12998178A priority Critical patent/JPS5557963A/en
Publication of JPS5557963A publication Critical patent/JPS5557963A/en
Publication of JPS6213698B2 publication Critical patent/JPS6213698B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To make it possible to display the internal state of an arithmetic circuit by simple circuit consitution by setting and resetting microinstructions from a maintenance unit by providing a stand-by register for control memory addresses.
CONSTITUTION: Address register 102 where control memory addresses stand by in every machine cycle is provided and in the beginning of display operation, microinstruction from a maintenance unit are set in microinstruction register 106 to establish a display routine. At the end of the display operation, the control memory is read by the output of address register 102 to reset the contents of the microinstruction register to a state before the display operation.
COPYRIGHT: (C)1980,JPO&Japio
JP12998178A 1978-10-24 1978-10-24 Information processor Granted JPS5557963A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12998178A JPS5557963A (en) 1978-10-24 1978-10-24 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12998178A JPS5557963A (en) 1978-10-24 1978-10-24 Information processor

Publications (2)

Publication Number Publication Date
JPS5557963A true JPS5557963A (en) 1980-04-30
JPS6213698B2 JPS6213698B2 (en) 1987-03-28

Family

ID=15023202

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12998178A Granted JPS5557963A (en) 1978-10-24 1978-10-24 Information processor

Country Status (1)

Country Link
JP (1) JPS5557963A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5383543A (en) * 1976-12-28 1978-07-24 Yokogawa Hokushin Electric Corp Microprogram control unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5383543A (en) * 1976-12-28 1978-07-24 Yokogawa Hokushin Electric Corp Microprogram control unit

Also Published As

Publication number Publication date
JPS6213698B2 (en) 1987-03-28

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