JPS5555571A - Semiconductor non volatile memory - Google Patents
Semiconductor non volatile memoryInfo
- Publication number
- JPS5555571A JPS5555571A JP12823078A JP12823078A JPS5555571A JP S5555571 A JPS5555571 A JP S5555571A JP 12823078 A JP12823078 A JP 12823078A JP 12823078 A JP12823078 A JP 12823078A JP S5555571 A JPS5555571 A JP S5555571A
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- layers
- becoming
- layer
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 238000009792 diffusion process Methods 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 230000010354 integration Effects 0.000 abstract 1
- 229910052750 molybdenum Inorganic materials 0.000 abstract 1
- 239000011733 molybdenum Substances 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
Landscapes
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
PURPOSE:To enable use of a semiconductor non volatile memory at large current or high voltage and high integration thereof by connecting MNOS transistor to read stored information from MNMOS non voltaile memory transistor Tr. CONSTITUTION:Memory transistors Q1, Q2 are formed on an N-type silicon substrate 1, and have diffusion layers 2, 4 becoming drains D1, D2, a diffusion layer 3 becoming a common source S, and an intercell insulating layer 5 of SiO2 formed thereat. These layers are coated by thermally oxidized film 6 of SiO2, and by second insulating film of si3N4. A molybdenum layer 7 becoming FG of the transistor Q1 is formed between the layers 2 and 3 with a contact hole 11 opened thereat and holes 9, 10 reaching the layers 2, 4. Electrodes 12, 13 pass through the holes 11 to become drain electrodes of the transistors Q1, Q2, respectively. The upper electrode 14 of the layer 7 becomes the control gate G1 of the transistor Q1, and an electrode 15 for coating the transistor Q2 becomes a gate G2 of the transistor Q2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12823078A JPS5555571A (en) | 1978-10-17 | 1978-10-17 | Semiconductor non volatile memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12823078A JPS5555571A (en) | 1978-10-17 | 1978-10-17 | Semiconductor non volatile memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5555571A true JPS5555571A (en) | 1980-04-23 |
Family
ID=14979701
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12823078A Pending JPS5555571A (en) | 1978-10-17 | 1978-10-17 | Semiconductor non volatile memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5555571A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5066992A (en) * | 1989-06-23 | 1991-11-19 | Atmel Corporation | Programmable and erasable MOS memory device |
| WO2001017025A3 (en) * | 1999-09-01 | 2001-06-07 | Infineon Technologies Ag | Semi-conductor component as a delaying device and use thereof. |
-
1978
- 1978-10-17 JP JP12823078A patent/JPS5555571A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5066992A (en) * | 1989-06-23 | 1991-11-19 | Atmel Corporation | Programmable and erasable MOS memory device |
| WO2001017025A3 (en) * | 1999-09-01 | 2001-06-07 | Infineon Technologies Ag | Semi-conductor component as a delaying device and use thereof. |
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