JPS5550634A - Preparation of semiconductor integrated circuit - Google Patents
Preparation of semiconductor integrated circuitInfo
- Publication number
- JPS5550634A JPS5550634A JP12481078A JP12481078A JPS5550634A JP S5550634 A JPS5550634 A JP S5550634A JP 12481078 A JP12481078 A JP 12481078A JP 12481078 A JP12481078 A JP 12481078A JP S5550634 A JPS5550634 A JP S5550634A
- Authority
- JP
- Japan
- Prior art keywords
- layers
- sio
- film
- birdbeak
- resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Element Separation (AREA)
Abstract
PURPOSE: To obtain an IC device, by moderating the limits of integration by the birdbeak of a SiO2 film, and by lightening the stress of distortion between SiO2 and Si3N4.
CONSTITUTION: Si3N421 is mounted to the interface of a p-type Si substrate 2 and a SiO2 film 3, and coated with a double-layer mask of Si3N44 and a resist 22, and a n-type ion shooting layers 23 are manufactured. The films 3, 21 are etching- opned, the resist 22 is removed and a SiO2 layers 6 for separation among elements are selectively prepared by thermal oxidation treatment. In this case, surface inversion preventive layers 25 by the ion shooting layers 23 are formed under the layers 6. Si3O4 films 4, 5 and a SiO2 film 24 are etching-removed, and one semiconductor element 8 is separated from other semiconductor elements 8 by the layers 6 according to the fixed method and made up. Since the length of birdbeak is not more than the thickness of the layers 6 in this method, the width of the layers 6 can remarkably be lessened as compared to conventional devices, this IC device can be compacted and element forming regions are not strained by the stress of distortion between Si3N424 and the substrate 2.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12481078A JPS5550634A (en) | 1978-10-11 | 1978-10-11 | Preparation of semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12481078A JPS5550634A (en) | 1978-10-11 | 1978-10-11 | Preparation of semiconductor integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5550634A true JPS5550634A (en) | 1980-04-12 |
JPS5628378B2 JPS5628378B2 (en) | 1981-07-01 |
Family
ID=14894672
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12481078A Granted JPS5550634A (en) | 1978-10-11 | 1978-10-11 | Preparation of semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5550634A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5348910A (en) * | 1991-12-24 | 1994-09-20 | Seiko Epson Corporation | Method of manufacturing a semiconductor device and the product thereby |
US7235460B2 (en) | 1993-07-30 | 2007-06-26 | Stmicroelectronics, Inc. | Method of forming active and isolation areas with split active patterning |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5444870A (en) * | 1977-09-16 | 1979-04-09 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Manufacture of semiconductor device |
-
1978
- 1978-10-11 JP JP12481078A patent/JPS5550634A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5444870A (en) * | 1977-09-16 | 1979-04-09 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Manufacture of semiconductor device |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5348910A (en) * | 1991-12-24 | 1994-09-20 | Seiko Epson Corporation | Method of manufacturing a semiconductor device and the product thereby |
US7235460B2 (en) | 1993-07-30 | 2007-06-26 | Stmicroelectronics, Inc. | Method of forming active and isolation areas with split active patterning |
Also Published As
Publication number | Publication date |
---|---|
JPS5628378B2 (en) | 1981-07-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS54142981A (en) | Manufacture of insulation gate type semiconductor device | |
JPS5550634A (en) | Preparation of semiconductor integrated circuit | |
JPS5792858A (en) | Semiconductor integrated circuit device and manufacture thereof | |
JPS5444870A (en) | Manufacture of semiconductor device | |
JPS5550636A (en) | Preparation of semiconductor device | |
JPS54107279A (en) | Semiconductor device | |
JPS5458381A (en) | Manufacture for semiconductor device | |
JPS55153325A (en) | Manufacture of semiconductor device | |
JPS57111042A (en) | Manufacture of semiconductor device | |
JPS54123878A (en) | Manufacture for semiconductor device | |
JPS5691430A (en) | Preparation of semiconductor device | |
JPS5534433A (en) | Preparation of semiconductor device | |
JPS5750451A (en) | Semiconductor | |
JPS5559738A (en) | Preparation of semiconductor device | |
JPS5527659A (en) | Method of manufacturing semiconductor device | |
JPS55110056A (en) | Semiconductor device | |
JPS5562750A (en) | Semiconductor integrated circuit device | |
JPS54139486A (en) | Manufacture of semiconductor device | |
JPS5762542A (en) | Manufacture of semiconductor device | |
JPS5527644A (en) | Multi-layer wiring type semiconductor device | |
JPS5382260A (en) | Production of semiconductor device | |
JPS5568650A (en) | Manufacturing method of semiconductor device | |
JPS5356981A (en) | Production of semiconductor device | |
JPS5527662A (en) | Method of manufacturing semiconductor device | |
JPS5271993A (en) | Production of semiconductor integrated circuit device |