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JPS5550634A - Preparation of semiconductor integrated circuit - Google Patents

Preparation of semiconductor integrated circuit

Info

Publication number
JPS5550634A
JPS5550634A JP12481078A JP12481078A JPS5550634A JP S5550634 A JPS5550634 A JP S5550634A JP 12481078 A JP12481078 A JP 12481078A JP 12481078 A JP12481078 A JP 12481078A JP S5550634 A JPS5550634 A JP S5550634A
Authority
JP
Japan
Prior art keywords
layers
sio
film
birdbeak
resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12481078A
Other languages
Japanese (ja)
Other versions
JPS5628378B2 (en
Inventor
Yutaka Yoriume
Kazushige Minegishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP12481078A priority Critical patent/JPS5550634A/en
Publication of JPS5550634A publication Critical patent/JPS5550634A/en
Publication of JPS5628378B2 publication Critical patent/JPS5628378B2/ja
Granted legal-status Critical Current

Links

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  • Element Separation (AREA)

Abstract

PURPOSE: To obtain an IC device, by moderating the limits of integration by the birdbeak of a SiO2 film, and by lightening the stress of distortion between SiO2 and Si3N4.
CONSTITUTION: Si3N421 is mounted to the interface of a p-type Si substrate 2 and a SiO2 film 3, and coated with a double-layer mask of Si3N44 and a resist 22, and a n-type ion shooting layers 23 are manufactured. The films 3, 21 are etching- opned, the resist 22 is removed and a SiO2 layers 6 for separation among elements are selectively prepared by thermal oxidation treatment. In this case, surface inversion preventive layers 25 by the ion shooting layers 23 are formed under the layers 6. Si3O4 films 4, 5 and a SiO2 film 24 are etching-removed, and one semiconductor element 8 is separated from other semiconductor elements 8 by the layers 6 according to the fixed method and made up. Since the length of birdbeak is not more than the thickness of the layers 6 in this method, the width of the layers 6 can remarkably be lessened as compared to conventional devices, this IC device can be compacted and element forming regions are not strained by the stress of distortion between Si3N424 and the substrate 2.
COPYRIGHT: (C)1980,JPO&Japio
JP12481078A 1978-10-11 1978-10-11 Preparation of semiconductor integrated circuit Granted JPS5550634A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12481078A JPS5550634A (en) 1978-10-11 1978-10-11 Preparation of semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12481078A JPS5550634A (en) 1978-10-11 1978-10-11 Preparation of semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPS5550634A true JPS5550634A (en) 1980-04-12
JPS5628378B2 JPS5628378B2 (en) 1981-07-01

Family

ID=14894672

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12481078A Granted JPS5550634A (en) 1978-10-11 1978-10-11 Preparation of semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS5550634A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5348910A (en) * 1991-12-24 1994-09-20 Seiko Epson Corporation Method of manufacturing a semiconductor device and the product thereby
US7235460B2 (en) 1993-07-30 2007-06-26 Stmicroelectronics, Inc. Method of forming active and isolation areas with split active patterning

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5444870A (en) * 1977-09-16 1979-04-09 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5444870A (en) * 1977-09-16 1979-04-09 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5348910A (en) * 1991-12-24 1994-09-20 Seiko Epson Corporation Method of manufacturing a semiconductor device and the product thereby
US7235460B2 (en) 1993-07-30 2007-06-26 Stmicroelectronics, Inc. Method of forming active and isolation areas with split active patterning

Also Published As

Publication number Publication date
JPS5628378B2 (en) 1981-07-01

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