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JPS553644A - Production of semiconductor device - Google Patents

Production of semiconductor device

Info

Publication number
JPS553644A
JPS553644A JP7542878A JP7542878A JPS553644A JP S553644 A JPS553644 A JP S553644A JP 7542878 A JP7542878 A JP 7542878A JP 7542878 A JP7542878 A JP 7542878A JP S553644 A JPS553644 A JP S553644A
Authority
JP
Japan
Prior art keywords
wafer
surface concentration
semiconductor substrate
controlled
sealed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7542878A
Other languages
Japanese (ja)
Inventor
Masaaki Kobayashi
Kenichi Goto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP7542878A priority Critical patent/JPS553644A/en
Publication of JPS553644A publication Critical patent/JPS553644A/en
Pending legal-status Critical Current

Links

Landscapes

  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

PURPOSE: To provide a semiconductor wafer with a desired surface concentration, the diffusion source vapor pressure is controlled by varying the ratio of the quantity of the vapor source to the volume of the sealed container.
CONSTITUTION: A semiconductor substrate 2 such as monocrystalline Si wafer is placed in a sealed container 1 together with diffusion source such as Ga-diffused polycrystalline Si wafer which is located under a boat 3. The container 1 is filled with innert gas such as Ar and sealed, then heated in an electric furnace 5. This process provides an impurity diffused layer having a uniform surface concentration on the semiconductor substrate 1. The surface concentration controlled to a desired degree eliminates the need for chemical polishing, resulting in a completely variation-free diffused layer.
COPYRIGHT: (C)1980,JPO&Japio
JP7542878A 1978-06-23 1978-06-23 Production of semiconductor device Pending JPS553644A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7542878A JPS553644A (en) 1978-06-23 1978-06-23 Production of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7542878A JPS553644A (en) 1978-06-23 1978-06-23 Production of semiconductor device

Publications (1)

Publication Number Publication Date
JPS553644A true JPS553644A (en) 1980-01-11

Family

ID=13575921

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7542878A Pending JPS553644A (en) 1978-06-23 1978-06-23 Production of semiconductor device

Country Status (1)

Country Link
JP (1) JPS553644A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6313398B1 (en) * 1999-06-24 2001-11-06 Shin-Etsu Chemical Co., Ltd. Ga-doped multi-crytsalline silicon, Ga-doped multi-crystalline silicon wafer and method for producing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6313398B1 (en) * 1999-06-24 2001-11-06 Shin-Etsu Chemical Co., Ltd. Ga-doped multi-crytsalline silicon, Ga-doped multi-crystalline silicon wafer and method for producing the same

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