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JPS553265A - Reception timing device for digital code - Google Patents

Reception timing device for digital code

Info

Publication number
JPS553265A
JPS553265A JP7602178A JP7602178A JPS553265A JP S553265 A JPS553265 A JP S553265A JP 7602178 A JP7602178 A JP 7602178A JP 7602178 A JP7602178 A JP 7602178A JP S553265 A JPS553265 A JP S553265A
Authority
JP
Japan
Prior art keywords
reception
reception timing
counter
internal state
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7602178A
Other languages
Japanese (ja)
Other versions
JPS6232854B2 (en
Inventor
Rikio Maruta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7602178A priority Critical patent/JPS553265A/en
Publication of JPS553265A publication Critical patent/JPS553265A/en
Publication of JPS6232854B2 publication Critical patent/JPS6232854B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To minimize the size of the digital communication device by constituting the reception timing device for the digital code which is given the simplified frame synchronizing function. CONSTITUTION:Reception timing counter 200 divides the clock pulse synchronized with the reception digital code row with the division ratio determined by the frame structure of the reception code row; and data delay circuit 300 makes parallel the frame synchronous pulse of the plural bits which is contained in the reception code row. In addition to these component units, the counting function is provided to show that counter 200 has reached the prescribed count value, along with reading exclusive memory 40 which delivers the new internal state signal and the advance control signal to be given to counter 200 by using the output of circuit 300 and the signal produced by delaying the internal state signal by one bit as part or whole of the input. Furthermore, register 500 is installed to give the delay of one bit to the output of internal state signal of memory 400 and then feed it back to the input of memory 1. Thus, the reception timing device is constituted.
JP7602178A 1978-06-22 1978-06-22 Reception timing device for digital code Granted JPS553265A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7602178A JPS553265A (en) 1978-06-22 1978-06-22 Reception timing device for digital code

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7602178A JPS553265A (en) 1978-06-22 1978-06-22 Reception timing device for digital code

Publications (2)

Publication Number Publication Date
JPS553265A true JPS553265A (en) 1980-01-11
JPS6232854B2 JPS6232854B2 (en) 1987-07-17

Family

ID=13593164

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7602178A Granted JPS553265A (en) 1978-06-22 1978-06-22 Reception timing device for digital code

Country Status (1)

Country Link
JP (1) JPS553265A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61139140A (en) * 1984-12-10 1986-06-26 Nec Corp Frame synchronizing circuit
JPS62239733A (en) * 1986-04-11 1987-10-20 Mitsubishi Electric Corp Data multiplex transmission system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61139140A (en) * 1984-12-10 1986-06-26 Nec Corp Frame synchronizing circuit
JPH0535618B2 (en) * 1984-12-10 1993-05-27 Nippon Electric Co
JPS62239733A (en) * 1986-04-11 1987-10-20 Mitsubishi Electric Corp Data multiplex transmission system

Also Published As

Publication number Publication date
JPS6232854B2 (en) 1987-07-17

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