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JPS5528550A - Servo circuit - Google Patents

Servo circuit

Info

Publication number
JPS5528550A
JPS5528550A JP10120178A JP10120178A JPS5528550A JP S5528550 A JPS5528550 A JP S5528550A JP 10120178 A JP10120178 A JP 10120178A JP 10120178 A JP10120178 A JP 10120178A JP S5528550 A JPS5528550 A JP S5528550A
Authority
JP
Japan
Prior art keywords
servo
phase
circuit
switched
control system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10120178A
Other languages
Japanese (ja)
Other versions
JPS6127826B2 (en
Inventor
Shinji Takada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP10120178A priority Critical patent/JPS5528550A/en
Publication of JPS5528550A publication Critical patent/JPS5528550A/en
Publication of JPS6127826B2 publication Critical patent/JPS6127826B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Control Of Velocity Or Acceleration (AREA)
  • Control Of Electric Motors In General (AREA)

Abstract

PURPOSE: To eliminate the servo disturbance occurring from switching of the servo loop by securing the 2nd comparison output nearly identical to the 1st comparison output when the 1st control system is switched to the 2nd control system.
CONSTITUTION: In the circuit which contains the servo loops of two systems for the head drum of VTR, delay circuit 16 is provided to give the delay of a fixed time to vertical synchronous signal VD which resets phase-locked loop (PLL) 11. As a result, phase difference ϕ2 is caused between signals CK and VD. At the same time, the phase difference ϕ1 between signals PG and FG of pulse generator 8 to detect the revolution speed of motor 6 and frequency generator 7 is set to ϕ2=ϕ1 when the phase locking is given through adjustment of variable resistance 16a. As a result, the error voltage of pahse comparator 15 becomes nearly identical to that of phase comparator 3 when switch circuit 4 is switched to contact b later, thus eliminating the servo disturbance.
COPYRIGHT: (C)1980,JPO&Japio
JP10120178A 1978-08-19 1978-08-19 Servo circuit Granted JPS5528550A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10120178A JPS5528550A (en) 1978-08-19 1978-08-19 Servo circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10120178A JPS5528550A (en) 1978-08-19 1978-08-19 Servo circuit

Publications (2)

Publication Number Publication Date
JPS5528550A true JPS5528550A (en) 1980-02-29
JPS6127826B2 JPS6127826B2 (en) 1986-06-27

Family

ID=14294308

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10120178A Granted JPS5528550A (en) 1978-08-19 1978-08-19 Servo circuit

Country Status (1)

Country Link
JP (1) JPS5528550A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4943968A (en) * 1972-07-28 1974-04-25

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4943968A (en) * 1972-07-28 1974-04-25

Also Published As

Publication number Publication date
JPS6127826B2 (en) 1986-06-27

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