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JPS5524477A - Integrated circuit - Google Patents

Integrated circuit

Info

Publication number
JPS5524477A
JPS5524477A JP9764778A JP9764778A JPS5524477A JP S5524477 A JPS5524477 A JP S5524477A JP 9764778 A JP9764778 A JP 9764778A JP 9764778 A JP9764778 A JP 9764778A JP S5524477 A JPS5524477 A JP S5524477A
Authority
JP
Japan
Prior art keywords
layer
film
hollows
substrates
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9764778A
Other languages
Japanese (ja)
Inventor
Yoshihiko Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP9764778A priority Critical patent/JPS5524477A/en
Publication of JPS5524477A publication Critical patent/JPS5524477A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE: For decreasing film consumption, to make an integrated circuit through the process consisting of depositing the Cu layer to be used for wiring on insulating film, providing on said film a hollows for the provision of semiconductor substrates by working said film and Cu layer, and extending to said hollows and connecting to said substrates said Cu layer.
CONSTITUTION: The Cu layer 32 having Au plating layer is deposited on polyimide film 31, and said film 31 and Cu layer 32 are worked into given shapes. At this time, said Cu layer 32 is extended into a plurality of hollows 33 and 33' in said film 31 and connected to the electrodes on the Si substrates 34 and 34' placed in said hollows 33 and 33' by said Au plating layer. Thereafter, the fitting thereof is made using epoxy resin 35. Thereby, the consumption of expensive insulating film 31 can be decreased to about 2/3 per substrate, and fitting density can be increased.
COPYRIGHT: (C)1980,JPO&Japio
JP9764778A 1978-08-09 1978-08-09 Integrated circuit Pending JPS5524477A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9764778A JPS5524477A (en) 1978-08-09 1978-08-09 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9764778A JPS5524477A (en) 1978-08-09 1978-08-09 Integrated circuit

Publications (1)

Publication Number Publication Date
JPS5524477A true JPS5524477A (en) 1980-02-21

Family

ID=14197890

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9764778A Pending JPS5524477A (en) 1978-08-09 1978-08-09 Integrated circuit

Country Status (1)

Country Link
JP (1) JPS5524477A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0515448U (en) * 1991-07-31 1993-02-26 住友金属工業株式会社 Ceramic package cage
JPH0661406A (en) * 1991-02-08 1994-03-04 Toshiba Corp Semiconductor device, its manufacture, and tape carrier
JPH07169794A (en) * 1993-12-15 1995-07-04 Nec Corp Film carrier package for semiconductor device
US5473199A (en) * 1992-03-02 1995-12-05 Fujitsu Limited Semiconductor device having a body with a carrier ring connected thereto

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5343475A (en) * 1976-10-01 1978-04-19 Seiko Epson Corp Flexible tape structure for gang bonding
JPS5349948A (en) * 1976-10-18 1978-05-06 Seiko Epson Corp Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5343475A (en) * 1976-10-01 1978-04-19 Seiko Epson Corp Flexible tape structure for gang bonding
JPS5349948A (en) * 1976-10-18 1978-05-06 Seiko Epson Corp Semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0661406A (en) * 1991-02-08 1994-03-04 Toshiba Corp Semiconductor device, its manufacture, and tape carrier
JPH0515448U (en) * 1991-07-31 1993-02-26 住友金属工業株式会社 Ceramic package cage
US5473199A (en) * 1992-03-02 1995-12-05 Fujitsu Limited Semiconductor device having a body with a carrier ring connected thereto
US5610080A (en) * 1992-03-02 1997-03-11 Fujitsu Ltd. Method for producing semiconductor device having a body with a carrier ring connected thereto
JPH07169794A (en) * 1993-12-15 1995-07-04 Nec Corp Film carrier package for semiconductor device

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