JPS55154829A - Logic circuit - Google Patents
Logic circuitInfo
- Publication number
- JPS55154829A JPS55154829A JP6299779A JP6299779A JPS55154829A JP S55154829 A JPS55154829 A JP S55154829A JP 6299779 A JP6299779 A JP 6299779A JP 6299779 A JP6299779 A JP 6299779A JP S55154829 A JPS55154829 A JP S55154829A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- circuits
- true
- complement
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
- H03K19/086—Emitter coupled logic
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Abstract
PURPOSE:To obtain a decoder circuit of current change-over circuit structure available for high-speed operation by leading each of a fixed number of input signals to one corresponding logic stage and then by supplying the true number and complement output of this logic stage to a group of current change-over type logic circuits. CONSTITUTION:Signal lines 10 and 11 to which input signals A and B are input are connected to gate circuits G7 and G8, and G9 and G10 and true outputs of circuits G7 and G9 are connected to output line 12 while the complement output of circuit G7 and the true output of circuit 10 are led to output line 13. Further, the true output of circuit G8 and the complement output of circuit G9 are connected to output line 14 and complement outputs of circuits G8 and G10 are further connected to output line 15 to generate logic outputs from output lines 12-15. Circuits G7 and G9, and G8 and G10 to which those signals A and B are input are made into a group of current change-over circuits consisting of transistors Q6-Q9 and current sources I3-I4 so as to enable a decoder circuit, composed of a current change-over circuit CML circuit, to operate at a high speed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6299779A JPS55154829A (en) | 1979-05-22 | 1979-05-22 | Logic circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6299779A JPS55154829A (en) | 1979-05-22 | 1979-05-22 | Logic circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS55154829A true JPS55154829A (en) | 1980-12-02 |
Family
ID=13216516
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6299779A Pending JPS55154829A (en) | 1979-05-22 | 1979-05-22 | Logic circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55154829A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5295135A (en) * | 1976-02-06 | 1977-08-10 | Nippon Telegr & Teleph Corp <Ntt> | Semi-conductor logic circuit |
-
1979
- 1979-05-22 JP JP6299779A patent/JPS55154829A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5295135A (en) * | 1976-02-06 | 1977-08-10 | Nippon Telegr & Teleph Corp <Ntt> | Semi-conductor logic circuit |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4424460A (en) | Apparatus and method for providing a logical exclusive OR/exclusive NOR function | |
JPS554691A (en) | Tree-type coupled logic circuit | |
DE3851001D1 (en) | Clock scheme for a VLSI system. | |
JPS5483341A (en) | Digital integrated circuit | |
JPS566535A (en) | Integrated circuit | |
EP0173799A3 (en) | Full adder circuit with sum and carry selection functions | |
EP0111262A3 (en) | Output multiplexer having one gate delay | |
GB747711A (en) | Improvements in digital calculating machines | |
TW344030B (en) | Integrated circuit having Schmitt input circuits | |
JPS55154829A (en) | Logic circuit | |
GB1295525A (en) | ||
JPS5446463A (en) | Pre-scaler | |
GB1312502A (en) | Logic circuits | |
JPS6432647A (en) | Semiconductor integrated circuit device | |
JPS6476221A (en) | Logical operating circuit | |
JPS6442720A (en) | Clock generating circuit | |
JPS572148A (en) | Ternary-to-binary code converting device | |
JPS5710532A (en) | Integrated circuit | |
JPS6472230A (en) | Bit inverter | |
JPS55147039A (en) | Logic circuit | |
JPS5572264A (en) | Information processor | |
JPS54149438A (en) | Sequence control circuit | |
JPS55145431A (en) | A/d converter | |
JPS57106229A (en) | Cmos multiinput storage circuit | |
JPS57109045A (en) | Data transfer speed converting circuit |