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JPS55150031A - Direct memory access unit - Google Patents

Direct memory access unit

Info

Publication number
JPS55150031A
JPS55150031A JP5777879A JP5777879A JPS55150031A JP S55150031 A JPS55150031 A JP S55150031A JP 5777879 A JP5777879 A JP 5777879A JP 5777879 A JP5777879 A JP 5777879A JP S55150031 A JPS55150031 A JP S55150031A
Authority
JP
Japan
Prior art keywords
transmission process
priority transmission
circuit
register
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5777879A
Other languages
Japanese (ja)
Inventor
Masaya Watanabe
Takeo Toda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP5777879A priority Critical patent/JPS55150031A/en
Publication of JPS55150031A publication Critical patent/JPS55150031A/en
Pending legal-status Critical Current

Links

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  • Bus Control (AREA)

Abstract

PURPOSE: To omit the remodeling of the hardware such as the increment of the cables although the priority transmission process words may be increased, by providing the priority transmission process detecting circuit and the word address switching circuit and then detecting the priority transmission process information of the main memory of the computer system.
CONSTITUTION: Priority transmission process address 10 of main memory 7 is always monitored via priority transmission process detecting circuit 12 provided to direct memory access unit 1 in order to detect the priority transmission process. At the same time, the switching is given via word address switching circuit 13 between circuit 12 and up-word address register 3 to be supplied to down-word register 6. When the priority transmission process is detected by circuit 12, the contact of circuit 13 is shifted to the side of contact 14a. Then the input signal to register 6 is used as output signal W of address 10, and data D corresponding to signal W is supplied to data register 5. And down-word address AD possessing the priority transmission process information is set in register 6, and address AD and data D are sent out to down-cyclic digital information unit 2.
COPYRIGHT: (C)1980,JPO&Japio
JP5777879A 1979-05-11 1979-05-11 Direct memory access unit Pending JPS55150031A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5777879A JPS55150031A (en) 1979-05-11 1979-05-11 Direct memory access unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5777879A JPS55150031A (en) 1979-05-11 1979-05-11 Direct memory access unit

Publications (1)

Publication Number Publication Date
JPS55150031A true JPS55150031A (en) 1980-11-21

Family

ID=13065320

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5777879A Pending JPS55150031A (en) 1979-05-11 1979-05-11 Direct memory access unit

Country Status (1)

Country Link
JP (1) JPS55150031A (en)

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