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JPS55146698A - Analog memory - Google Patents

Analog memory

Info

Publication number
JPS55146698A
JPS55146698A JP5343279A JP5343279A JPS55146698A JP S55146698 A JPS55146698 A JP S55146698A JP 5343279 A JP5343279 A JP 5343279A JP 5343279 A JP5343279 A JP 5343279A JP S55146698 A JPS55146698 A JP S55146698A
Authority
JP
Japan
Prior art keywords
signal
line
terminal
input terminal
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5343279A
Other languages
Japanese (ja)
Inventor
Takuya Imaide
Tomomitsu Azeyanagi
Michio Masuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP5343279A priority Critical patent/JPS55146698A/en
Publication of JPS55146698A publication Critical patent/JPS55146698A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to attain line random access suitable for video signal processing by providing analog memory elements, arranged in a line, a line asigning method and an access method.
CONSTITUTION: Signal II is inputted to vertical data input terminal 411 of shift register 111, and clock signals I are also input to the vertical clock terminal as many as (n) to select an n-th line. Next, write period signal input terminal 911 is applied with signal III increasing in level to high after the n-th line is selected, horizontal data input terminal 412 of shift register 112 and horizontal clock terminal 312 are further applied with signal IV and signal V respectively, so that a signal input to signal input terminal 511 will sequentially be stored in the n-th line of memories. In read operation, while terminal 911 is held low, read period signal input terminal 912 is applied with signal III to drive register 112 in the same way, so tat a read signal will be obtained from signal output terminal 512.
COPYRIGHT: (C)1980,JPO&Japio
JP5343279A 1979-05-02 1979-05-02 Analog memory Pending JPS55146698A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5343279A JPS55146698A (en) 1979-05-02 1979-05-02 Analog memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5343279A JPS55146698A (en) 1979-05-02 1979-05-02 Analog memory

Publications (1)

Publication Number Publication Date
JPS55146698A true JPS55146698A (en) 1980-11-15

Family

ID=12942675

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5343279A Pending JPS55146698A (en) 1979-05-02 1979-05-02 Analog memory

Country Status (1)

Country Link
JP (1) JPS55146698A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0721793A (en) * 1993-05-24 1995-01-24 Tektronix Inc Analog storage array

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0721793A (en) * 1993-05-24 1995-01-24 Tektronix Inc Analog storage array

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