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JPS55138841A - Method of forming pattern on semiconductor element - Google Patents

Method of forming pattern on semiconductor element

Info

Publication number
JPS55138841A
JPS55138841A JP4710779A JP4710779A JPS55138841A JP S55138841 A JPS55138841 A JP S55138841A JP 4710779 A JP4710779 A JP 4710779A JP 4710779 A JP4710779 A JP 4710779A JP S55138841 A JPS55138841 A JP S55138841A
Authority
JP
Japan
Prior art keywords
wax
wafer
semiconductor element
pattern
solvent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4710779A
Other languages
Japanese (ja)
Inventor
Takao Watanabe
Takahiro Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Meidensha Electric Manufacturing Co Ltd
Original Assignee
Meidensha Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meidensha Electric Manufacturing Co Ltd filed Critical Meidensha Electric Manufacturing Co Ltd
Priority to JP4710779A priority Critical patent/JPS55138841A/en
Publication of JPS55138841A publication Critical patent/JPS55138841A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To largely omit the number of processing steps in a method of forming a pattern on a semiconductor element and to form an accurate and preferable pattern thereon by screen printing a mask material made of wax and solvent thereon and then deeply etching the masked wafer. CONSTITUTION:A wax material 6 made of wax such as apiezon series wax and solvent such as butylcarbylacetate series solvent is screen printed as a mask agent on a semiconductor element wafer 1. Then, the wafer 1 is dried and then deeply etched to form a pattern 4 thereon. The wax material 6 is then removed therefrom. It is noted that after an oxide film is formed on the wafer 1, the wax material 6 is screen printed thereon as required.
JP4710779A 1979-04-16 1979-04-16 Method of forming pattern on semiconductor element Pending JPS55138841A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4710779A JPS55138841A (en) 1979-04-16 1979-04-16 Method of forming pattern on semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4710779A JPS55138841A (en) 1979-04-16 1979-04-16 Method of forming pattern on semiconductor element

Publications (1)

Publication Number Publication Date
JPS55138841A true JPS55138841A (en) 1980-10-30

Family

ID=12765944

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4710779A Pending JPS55138841A (en) 1979-04-16 1979-04-16 Method of forming pattern on semiconductor element

Country Status (1)

Country Link
JP (1) JPS55138841A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0527744A1 (en) * 1990-04-30 1993-02-24 Bell Communications Research, Inc. Patterning method for epitaxial lift-off processing
US6872320B2 (en) 2001-04-19 2005-03-29 Xerox Corporation Method for printing etch masks using phase-change materials
US7223700B2 (en) 2002-06-27 2007-05-29 Palo Alto Research Center Incorporated Method for fabricating fine features by jet-printing and surface treatment

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0527744A1 (en) * 1990-04-30 1993-02-24 Bell Communications Research, Inc. Patterning method for epitaxial lift-off processing
EP0527744A4 (en) * 1990-04-30 1993-11-03 Bell Communications Research, Inc. Patterning method for epitaxial lift-off processing
US6872320B2 (en) 2001-04-19 2005-03-29 Xerox Corporation Method for printing etch masks using phase-change materials
US7033516B2 (en) 2001-04-19 2006-04-25 Xerox Corporation Inexpensive fabrication of large-area pixel arrays for displays and sensors
EP1251398A3 (en) * 2001-04-19 2009-09-23 Xerox Corporation Method for printing etch masks using phase-change materials
EP1251398B1 (en) * 2001-04-19 2016-01-13 Xerox Corporation Method of patterning a thin film layer using phase-change materials
US7223700B2 (en) 2002-06-27 2007-05-29 Palo Alto Research Center Incorporated Method for fabricating fine features by jet-printing and surface treatment

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