JPS55134964A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS55134964A JPS55134964A JP4336179A JP4336179A JPS55134964A JP S55134964 A JPS55134964 A JP S55134964A JP 4336179 A JP4336179 A JP 4336179A JP 4336179 A JP4336179 A JP 4336179A JP S55134964 A JPS55134964 A JP S55134964A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- polycrystalline
- layers
- selectively
- sio2
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 5
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 abstract 2
- 238000009792 diffusion process Methods 0.000 abstract 2
- 229910021339 platinum silicide Inorganic materials 0.000 abstract 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000002955 isolation Methods 0.000 abstract 1
- 230000008018 melting Effects 0.000 abstract 1
- 238000002844 melting Methods 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 abstract 1
- 239000002184 metal Substances 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 229910021332 silicide Inorganic materials 0.000 abstract 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/62—Electrodes ohmically coupled to a semiconductor
Landscapes
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
Abstract
PURPOSE:To prevent the formation of pn-junction between a doped polycrystalline Si wiring layer and a reverse conducting type diffusion layer by interposing a metal silicide layer with high melting point between a doped polycrystalline Si wiring layer and a reverse conducting type diffusion layer and by making a good ohmic connection. CONSTITUTION:p-Type layers 15, 16 and n<+>-layers 17, 18 are formed in an n- epitaxial layer surrounded by an n<+>-buried layer and a p<+>-isolation layer. Selective windows 211, 212 and 213 are provided on an SiO2 film 20 and platinum silicide 23 is selectively sticked to the window 213 of the p-layer 15. Then, an n-type polycrystalline Si 24 and an SiO2 25 are stacked and after selectively removing the film 25 by an Si3N4 mask 26, selective oxidation is made to form an SiO2 film 27 and polycrystalline Si layers 28, 29 and 30. Electrodes 32, 33 and 34 are formed by removing the masks 26, by covering with a PSG31 and by selectively cutting the windows. By this composition, a good ohmic connection is made for the polycrystalline Si electrode 28 and the p-layer 16 by the platinum silicide layer 23 and fixed element functions are shown without forming pn-junction and a good and high integrated device is formed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4336179A JPS55134964A (en) | 1979-04-10 | 1979-04-10 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4336179A JPS55134964A (en) | 1979-04-10 | 1979-04-10 | Semiconductor device and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS55134964A true JPS55134964A (en) | 1980-10-21 |
Family
ID=12661708
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4336179A Pending JPS55134964A (en) | 1979-04-10 | 1979-04-10 | Semiconductor device and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55134964A (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58216463A (en) * | 1982-06-07 | 1983-12-16 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | bipolar transistor |
US4476482A (en) * | 1981-05-29 | 1984-10-09 | Texas Instruments Incorporated | Silicide contacts for CMOS devices |
US4528582A (en) * | 1983-09-21 | 1985-07-09 | General Electric Company | Interconnection structure for polycrystalline silicon resistor and methods of making same |
US4621276A (en) * | 1984-05-24 | 1986-11-04 | Texas Instruments Incorporated | Buried contacts for N and P channel devices in an SOI-CMOS process using a single N+polycrystalline silicon layer |
JPS6218069A (en) * | 1985-07-16 | 1987-01-27 | Toshiba Corp | semiconductor equipment |
US4677735A (en) * | 1984-05-24 | 1987-07-07 | Texas Instruments Incorporated | Method of providing buried contacts for N and P channel devices in an SOI-CMOS process using a single N+polycrystalline silicon layer |
US4824799A (en) * | 1985-01-17 | 1989-04-25 | Kabushiki Kaisha Toshiba | Method of making a bipolar semiconductor device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5326664A (en) * | 1976-08-25 | 1978-03-11 | Oki Electric Ind Co Ltd | Formation of ohmic contact |
-
1979
- 1979-04-10 JP JP4336179A patent/JPS55134964A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5326664A (en) * | 1976-08-25 | 1978-03-11 | Oki Electric Ind Co Ltd | Formation of ohmic contact |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4476482A (en) * | 1981-05-29 | 1984-10-09 | Texas Instruments Incorporated | Silicide contacts for CMOS devices |
JPS58216463A (en) * | 1982-06-07 | 1983-12-16 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | bipolar transistor |
US4528582A (en) * | 1983-09-21 | 1985-07-09 | General Electric Company | Interconnection structure for polycrystalline silicon resistor and methods of making same |
US4621276A (en) * | 1984-05-24 | 1986-11-04 | Texas Instruments Incorporated | Buried contacts for N and P channel devices in an SOI-CMOS process using a single N+polycrystalline silicon layer |
US4677735A (en) * | 1984-05-24 | 1987-07-07 | Texas Instruments Incorporated | Method of providing buried contacts for N and P channel devices in an SOI-CMOS process using a single N+polycrystalline silicon layer |
US4824799A (en) * | 1985-01-17 | 1989-04-25 | Kabushiki Kaisha Toshiba | Method of making a bipolar semiconductor device |
JPS6218069A (en) * | 1985-07-16 | 1987-01-27 | Toshiba Corp | semiconductor equipment |
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