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JPS55134964A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS55134964A
JPS55134964A JP4336179A JP4336179A JPS55134964A JP S55134964 A JPS55134964 A JP S55134964A JP 4336179 A JP4336179 A JP 4336179A JP 4336179 A JP4336179 A JP 4336179A JP S55134964 A JPS55134964 A JP S55134964A
Authority
JP
Japan
Prior art keywords
layer
polycrystalline
layers
selectively
sio2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4336179A
Other languages
Japanese (ja)
Inventor
Jiro Oshima
Masaharu Aoyama
Seiji Yasuda
Shunichi Kai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP4336179A priority Critical patent/JPS55134964A/en
Publication of JPS55134964A publication Critical patent/JPS55134964A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/62Electrodes ohmically coupled to a semiconductor

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To prevent the formation of pn-junction between a doped polycrystalline Si wiring layer and a reverse conducting type diffusion layer by interposing a metal silicide layer with high melting point between a doped polycrystalline Si wiring layer and a reverse conducting type diffusion layer and by making a good ohmic connection. CONSTITUTION:p-Type layers 15, 16 and n<+>-layers 17, 18 are formed in an n- epitaxial layer surrounded by an n<+>-buried layer and a p<+>-isolation layer. Selective windows 211, 212 and 213 are provided on an SiO2 film 20 and platinum silicide 23 is selectively sticked to the window 213 of the p-layer 15. Then, an n-type polycrystalline Si 24 and an SiO2 25 are stacked and after selectively removing the film 25 by an Si3N4 mask 26, selective oxidation is made to form an SiO2 film 27 and polycrystalline Si layers 28, 29 and 30. Electrodes 32, 33 and 34 are formed by removing the masks 26, by covering with a PSG31 and by selectively cutting the windows. By this composition, a good ohmic connection is made for the polycrystalline Si electrode 28 and the p-layer 16 by the platinum silicide layer 23 and fixed element functions are shown without forming pn-junction and a good and high integrated device is formed.
JP4336179A 1979-04-10 1979-04-10 Semiconductor device and manufacture thereof Pending JPS55134964A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4336179A JPS55134964A (en) 1979-04-10 1979-04-10 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4336179A JPS55134964A (en) 1979-04-10 1979-04-10 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS55134964A true JPS55134964A (en) 1980-10-21

Family

ID=12661708

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4336179A Pending JPS55134964A (en) 1979-04-10 1979-04-10 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS55134964A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58216463A (en) * 1982-06-07 1983-12-16 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション bipolar transistor
US4476482A (en) * 1981-05-29 1984-10-09 Texas Instruments Incorporated Silicide contacts for CMOS devices
US4528582A (en) * 1983-09-21 1985-07-09 General Electric Company Interconnection structure for polycrystalline silicon resistor and methods of making same
US4621276A (en) * 1984-05-24 1986-11-04 Texas Instruments Incorporated Buried contacts for N and P channel devices in an SOI-CMOS process using a single N+polycrystalline silicon layer
JPS6218069A (en) * 1985-07-16 1987-01-27 Toshiba Corp semiconductor equipment
US4677735A (en) * 1984-05-24 1987-07-07 Texas Instruments Incorporated Method of providing buried contacts for N and P channel devices in an SOI-CMOS process using a single N+polycrystalline silicon layer
US4824799A (en) * 1985-01-17 1989-04-25 Kabushiki Kaisha Toshiba Method of making a bipolar semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5326664A (en) * 1976-08-25 1978-03-11 Oki Electric Ind Co Ltd Formation of ohmic contact

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5326664A (en) * 1976-08-25 1978-03-11 Oki Electric Ind Co Ltd Formation of ohmic contact

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4476482A (en) * 1981-05-29 1984-10-09 Texas Instruments Incorporated Silicide contacts for CMOS devices
JPS58216463A (en) * 1982-06-07 1983-12-16 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション bipolar transistor
US4528582A (en) * 1983-09-21 1985-07-09 General Electric Company Interconnection structure for polycrystalline silicon resistor and methods of making same
US4621276A (en) * 1984-05-24 1986-11-04 Texas Instruments Incorporated Buried contacts for N and P channel devices in an SOI-CMOS process using a single N+polycrystalline silicon layer
US4677735A (en) * 1984-05-24 1987-07-07 Texas Instruments Incorporated Method of providing buried contacts for N and P channel devices in an SOI-CMOS process using a single N+polycrystalline silicon layer
US4824799A (en) * 1985-01-17 1989-04-25 Kabushiki Kaisha Toshiba Method of making a bipolar semiconductor device
JPS6218069A (en) * 1985-07-16 1987-01-27 Toshiba Corp semiconductor equipment

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