JPS55110323A - Method and device for bus use control - Google Patents
Method and device for bus use controlInfo
- Publication number
- JPS55110323A JPS55110323A JP1708679A JP1708679A JPS55110323A JP S55110323 A JPS55110323 A JP S55110323A JP 1708679 A JP1708679 A JP 1708679A JP 1708679 A JP1708679 A JP 1708679A JP S55110323 A JPS55110323 A JP S55110323A
- Authority
- JP
- Japan
- Prior art keywords
- bus
- signal
- gate unit
- outputted
- counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Multi Processors (AREA)
- Bus Control (AREA)
Abstract
PURPOSE: To realize the bus use control of processor systems, using an parallel type common bus, in a simple and easy-to-extend method by employing a fundamental clock generator, reset unit, counter, comparator, and gate unit.
CONSTITUTION: When bus request signal RQi is outputted from processor (i), bus-use request signal BRQi is outputted. When bus-use permission signal PMTi is returned from bus-use controller 100, gate unit 104 is opened. Counter 102, on the other hand, counts fundamental clocks CLK while synchronizing with the counter of another processor by synchronizing signal TE. When its count value agrees with a characteristic number preset to preset unit 101, a signal is outputted by comparator 103 and inputted via gate unit 104WFF2 to output bus-use signal BSY and also to suppress bus request signal BRQi while closing gate unit 104. In this way, processors can be incorporated in the precedence, so that the number of processors can easily be increased.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54017086A JPS5913763B2 (en) | 1979-02-16 | 1979-02-16 | Bus usage control method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54017086A JPS5913763B2 (en) | 1979-02-16 | 1979-02-16 | Bus usage control method and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55110323A true JPS55110323A (en) | 1980-08-25 |
| JPS5913763B2 JPS5913763B2 (en) | 1984-03-31 |
Family
ID=11934165
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP54017086A Expired JPS5913763B2 (en) | 1979-02-16 | 1979-02-16 | Bus usage control method and device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5913763B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58119069A (en) * | 1982-01-06 | 1983-07-15 | Hitachi Ltd | Decentralized contention control system |
| JPH02500306A (en) * | 1986-12-23 | 1990-02-01 | ベル、コミュニケーションズ、リサーチ、インコーポレーテッド | Parallel processing state consistency |
-
1979
- 1979-02-16 JP JP54017086A patent/JPS5913763B2/en not_active Expired
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58119069A (en) * | 1982-01-06 | 1983-07-15 | Hitachi Ltd | Decentralized contention control system |
| JPH0343658B2 (en) * | 1982-01-06 | 1991-07-03 | Hitachi Ltd | |
| JPH02500306A (en) * | 1986-12-23 | 1990-02-01 | ベル、コミュニケーションズ、リサーチ、インコーポレーテッド | Parallel processing state consistency |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5913763B2 (en) | 1984-03-31 |
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