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JPS5498138A - Input/output control system - Google Patents

Input/output control system

Info

Publication number
JPS5498138A
JPS5498138A JP430778A JP430778A JPS5498138A JP S5498138 A JPS5498138 A JP S5498138A JP 430778 A JP430778 A JP 430778A JP 430778 A JP430778 A JP 430778A JP S5498138 A JPS5498138 A JP S5498138A
Authority
JP
Japan
Prior art keywords
chain
channel control
address
ccb
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP430778A
Other languages
Japanese (ja)
Inventor
Yukiro Shiraokawa
Tsutomu Sakamoto
Keizo Aoyanagi
Michio Arai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP430778A priority Critical patent/JPS5498138A/en
Publication of JPS5498138A publication Critical patent/JPS5498138A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To indicate the channel control word address of the chain destination by setting a prescribed bit of the channel control word in the channel control block which had control information for a peripheral device.
CONSTITUTION: A bit if chain 2 exists in channel control word CCW in channel control block CCB. Chain 2 indicates the next processing with a priority lower than chain 1. When chain 2 is set, the storage start address of CCB of the chain destination is indicated by chain address in CCB. Chain address 2 in CCB is indicated in an absolute address. When chain 1 and chain 2 are set simultaneously, the processing of chain 1 and the processing of chain 2 are performed continuously in order.
COPYRIGHT: (C)1979,JPO&Japio
JP430778A 1978-01-20 1978-01-20 Input/output control system Pending JPS5498138A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP430778A JPS5498138A (en) 1978-01-20 1978-01-20 Input/output control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP430778A JPS5498138A (en) 1978-01-20 1978-01-20 Input/output control system

Publications (1)

Publication Number Publication Date
JPS5498138A true JPS5498138A (en) 1979-08-02

Family

ID=11580831

Family Applications (1)

Application Number Title Priority Date Filing Date
JP430778A Pending JPS5498138A (en) 1978-01-20 1978-01-20 Input/output control system

Country Status (1)

Country Link
JP (1) JPS5498138A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0024927A2 (en) * 1979-08-31 1981-03-11 Kabushiki Kaisha Toshiba Surface acoustic wave resonator device
JP2013536487A (en) * 2010-06-23 2013-09-19 インターナショナル・ビジネス・マシーンズ・コーポレーション Load instruction for communication with the adapter

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52155024A (en) * 1976-04-30 1977-12-23 Ibm Data processing system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52155024A (en) * 1976-04-30 1977-12-23 Ibm Data processing system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0024927A2 (en) * 1979-08-31 1981-03-11 Kabushiki Kaisha Toshiba Surface acoustic wave resonator device
JP2013536487A (en) * 2010-06-23 2013-09-19 インターナショナル・ビジネス・マシーンズ・コーポレーション Load instruction for communication with the adapter

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