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JPS5483341A - Digital integrated circuit - Google Patents

Digital integrated circuit

Info

Publication number
JPS5483341A
JPS5483341A JP15130777A JP15130777A JPS5483341A JP S5483341 A JPS5483341 A JP S5483341A JP 15130777 A JP15130777 A JP 15130777A JP 15130777 A JP15130777 A JP 15130777A JP S5483341 A JPS5483341 A JP S5483341A
Authority
JP
Japan
Prior art keywords
input
output terminals
integrated circuit
terminals
gates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15130777A
Other languages
English (en)
Other versions
JPS6118778B2 (ja
Inventor
Hiroshi Mayumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15130777A priority Critical patent/JPS5483341A/ja
Priority to US05/969,891 priority patent/US4267463A/en
Publication of JPS5483341A publication Critical patent/JPS5483341A/ja
Publication of JPS6118778B2 publication Critical patent/JPS6118778B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318516—Test of programmable logic devices [PLDs]

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
JP15130777A 1977-12-15 1977-12-15 Digital integrated circuit Granted JPS5483341A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP15130777A JPS5483341A (en) 1977-12-15 1977-12-15 Digital integrated circuit
US05/969,891 US4267463A (en) 1977-12-15 1978-12-15 Digital integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15130777A JPS5483341A (en) 1977-12-15 1977-12-15 Digital integrated circuit

Related Child Applications (3)

Application Number Title Priority Date Filing Date
JP59164640A Division JPS6095370A (ja) 1984-08-06 1984-08-06 集積回路装置
JP59164639A Division JPS6094532A (ja) 1984-08-06 1984-08-06 プログラマブルロジツクアレイ回路
JP60221271A Division JPS61180331A (ja) 1985-10-04 1985-10-04 集積回路装置

Publications (2)

Publication Number Publication Date
JPS5483341A true JPS5483341A (en) 1979-07-03
JPS6118778B2 JPS6118778B2 (ja) 1986-05-14

Family

ID=15515792

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15130777A Granted JPS5483341A (en) 1977-12-15 1977-12-15 Digital integrated circuit

Country Status (2)

Country Link
US (1) US4267463A (ja)
JP (1) JPS5483341A (ja)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57203137A (en) * 1981-06-04 1982-12-13 Ibm Logic array
JPS58121447A (ja) * 1982-01-13 1983-07-19 Nec Corp 論理集積回路
JPS6094532A (ja) * 1984-08-06 1985-05-27 Nec Corp プログラマブルロジツクアレイ回路
JPH0683591A (ja) * 1992-09-07 1994-03-25 Nec Corp 浮動小数点乗算器とそのテスト方式
JPH08256053A (ja) * 1985-12-06 1996-10-01 Advanced Micro Devices Inc プログラム可能論理アレイ装置
US6138177A (en) * 1996-12-31 2000-10-24 Opti Inc. System and method of pin programming and configuration

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4431928A (en) * 1981-06-22 1984-02-14 Hewlett-Packard Company Symmetrical programmable logic array
US4422072A (en) * 1981-07-30 1983-12-20 Signetics Corporation Field programmable logic array circuit
US4489417A (en) * 1982-11-24 1984-12-18 International Business Machines Corporation Multi-level communication circuitry for communicating digital signals between integrated circuits
US4525641A (en) * 1982-12-10 1985-06-25 International Business Machines Corporation Flip-flop programmer using cascaded logic arrays
US4602210A (en) * 1984-12-28 1986-07-22 General Electric Company Multiplexed-access scan testable integrated circuit
US4758746A (en) * 1985-08-12 1988-07-19 Monolithic Memories, Inc. Programmable logic array with added array of gates and added output routing flexibility
JPS6243764A (ja) * 1985-08-21 1987-02-25 Nec Corp バス・ステ−ト制御回路
JPH0756503B2 (ja) * 1985-11-26 1995-06-14 株式会社日立製作所 論理回路診断方法
US4758747A (en) * 1986-05-30 1988-07-19 Advanced Micro Devices, Inc. Programmable logic device with buried registers selectively multiplexed with output registers to ports, and preload circuitry therefor
US5477165A (en) * 1986-09-19 1995-12-19 Actel Corporation Programmable logic module and architecture for field programmable gate array device
JPH01270683A (ja) * 1988-04-22 1989-10-27 Mitsubishi Electric Corp 半導体集積回路
US5479649A (en) * 1992-05-01 1995-12-26 Advanced Micro Devices, Inc. Method and apparatus for forming a logical combination of signals from diagnostic nodes in an IC chip for passive observation at a dedicated diagnostic pin
US5625631A (en) * 1996-04-26 1997-04-29 International Business Machines Corporation Pass through mode for multi-chip-module die
US6691267B1 (en) 1997-06-10 2004-02-10 Altera Corporation Technique to test an integrated circuit using fewer pins
JP2012112788A (ja) * 2010-11-24 2012-06-14 Seiko Instruments Inc テストモード設定回路
KR102687581B1 (ko) * 2018-12-31 2024-07-24 에스케이하이닉스 주식회사 클럭 생성 회로 및 이를 포함하는 메모리 장치

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3818202A (en) * 1973-02-20 1974-06-18 Sperry Rand Corp Binary bypassable arithmetic linear module

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57203137A (en) * 1981-06-04 1982-12-13 Ibm Logic array
JPH0218497B2 (ja) * 1981-06-04 1990-04-25 Intaanashonaru Bijinesu Mashiinzu Corp
JPS58121447A (ja) * 1982-01-13 1983-07-19 Nec Corp 論理集積回路
JPH033251B2 (ja) * 1982-01-13 1991-01-18 Nippon Electric Co
JPS6094532A (ja) * 1984-08-06 1985-05-27 Nec Corp プログラマブルロジツクアレイ回路
JPH0137045B2 (ja) * 1984-08-06 1989-08-03 Nippon Electric Co
JPH08256053A (ja) * 1985-12-06 1996-10-01 Advanced Micro Devices Inc プログラム可能論理アレイ装置
JPH0683591A (ja) * 1992-09-07 1994-03-25 Nec Corp 浮動小数点乗算器とそのテスト方式
US6138177A (en) * 1996-12-31 2000-10-24 Opti Inc. System and method of pin programming and configuration

Also Published As

Publication number Publication date
US4267463A (en) 1981-05-12
JPS6118778B2 (ja) 1986-05-14

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