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JPS5534741A - Micro computer input circuit - Google Patents

Micro computer input circuit

Info

Publication number
JPS5534741A
JPS5534741A JP10750678A JP10750678A JPS5534741A JP S5534741 A JPS5534741 A JP S5534741A JP 10750678 A JP10750678 A JP 10750678A JP 10750678 A JP10750678 A JP 10750678A JP S5534741 A JPS5534741 A JP S5534741A
Authority
JP
Japan
Prior art keywords
output
level
micro computer
terminals
key matrix
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10750678A
Other languages
Japanese (ja)
Inventor
Toshifumi Shibuya
Yoshimi Iso
Shigeki Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10750678A priority Critical patent/JPS5534741A/en
Publication of JPS5534741A publication Critical patent/JPS5534741A/en
Pending legal-status Critical Current

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  • Input From Keyboards Or The Like (AREA)

Abstract

PURPOSE: To increase the number of key inputs by connecting the AND circuit between the column line, which is provided besides column lines of a key matrix circuit, and the output of an input signal other than the key matrix to the output of the key matrix circuit.
CONSTITUTION: Level "1" id outputted to output terminals 10, 11, 12, 13 and 44 in order in time division. When output terminal 10, 11, 12, or 13 is levle "1", terminal 44 is level "0", so that the output of AND circuits 39 to 42 becomes level "0", and the output of key matrix circuit 38 is applied to terminals 14 to 17 of micro computer 1. Then, since terminals 10, 11, 12 and 13 are level "0" when terminal 44 is level "1", output signals of encoder circuit 43 are applied to terminals 14 to 17 of micro computer 1 through AND circuits 39 to 42.
COPYRIGHT: (C)1980,JPO&Japio
JP10750678A 1978-09-04 1978-09-04 Micro computer input circuit Pending JPS5534741A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10750678A JPS5534741A (en) 1978-09-04 1978-09-04 Micro computer input circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10750678A JPS5534741A (en) 1978-09-04 1978-09-04 Micro computer input circuit

Publications (1)

Publication Number Publication Date
JPS5534741A true JPS5534741A (en) 1980-03-11

Family

ID=14460926

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10750678A Pending JPS5534741A (en) 1978-09-04 1978-09-04 Micro computer input circuit

Country Status (1)

Country Link
JP (1) JPS5534741A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6334626A (en) * 1986-07-29 1988-02-15 Shinko Seisakusho:Kk Key input device
US5381142A (en) * 1993-02-19 1995-01-10 Thomson Consumer Electronics, Inc. Remote control unit having additional keys serviced via an interrupt

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6334626A (en) * 1986-07-29 1988-02-15 Shinko Seisakusho:Kk Key input device
US5381142A (en) * 1993-02-19 1995-01-10 Thomson Consumer Electronics, Inc. Remote control unit having additional keys serviced via an interrupt

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