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JPS5480636A - Data processor - Google Patents

Data processor

Info

Publication number
JPS5480636A
JPS5480636A JP14835877A JP14835877A JPS5480636A JP S5480636 A JPS5480636 A JP S5480636A JP 14835877 A JP14835877 A JP 14835877A JP 14835877 A JP14835877 A JP 14835877A JP S5480636 A JPS5480636 A JP S5480636A
Authority
JP
Japan
Prior art keywords
value
logic circuit
bus
digital information
slicer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14835877A
Other languages
Japanese (ja)
Inventor
Masayuki Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14835877A priority Critical patent/JPS5480636A/en
Publication of JPS5480636A publication Critical patent/JPS5480636A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)

Abstract

PURPOSE: To utilize the bus construction logically in multiplicity, which is physically limited, by adopting the multi value logic circuit to the bus line for data delivery.
CONSTITUTION: When two value digital information is parallely inputted to the input terminals 51 and 5b of the mixer (multi-value logic circuit) 5, the multi signal is transferred to the slicer (multi logic circuit) 6 through the bus line 4. The slicer converts the multi-value signal again into the binary digital information, that is, input and outputs it to the terminals 6a and 6b. Thus, the number of bus lines can logically extended and the through-put time of the entire system can be increased.
COPYRIGHT: (C)1979,JPO&Japio
JP14835877A 1977-12-10 1977-12-10 Data processor Pending JPS5480636A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14835877A JPS5480636A (en) 1977-12-10 1977-12-10 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14835877A JPS5480636A (en) 1977-12-10 1977-12-10 Data processor

Publications (1)

Publication Number Publication Date
JPS5480636A true JPS5480636A (en) 1979-06-27

Family

ID=15450961

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14835877A Pending JPS5480636A (en) 1977-12-10 1977-12-10 Data processor

Country Status (1)

Country Link
JP (1) JPS5480636A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61107415A (en) * 1984-10-26 1986-05-26 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Interface unit
JPH0263127U (en) * 1988-10-31 1990-05-11

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61107415A (en) * 1984-10-26 1986-05-26 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Interface unit
JPH0263127U (en) * 1988-10-31 1990-05-11

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