[go: up one dir, main page]

JPS5475233A - Memory controller - Google Patents

Memory controller

Info

Publication number
JPS5475233A
JPS5475233A JP14291577A JP14291577A JPS5475233A JP S5475233 A JPS5475233 A JP S5475233A JP 14291577 A JP14291577 A JP 14291577A JP 14291577 A JP14291577 A JP 14291577A JP S5475233 A JPS5475233 A JP S5475233A
Authority
JP
Japan
Prior art keywords
memory
circuit
varies
cycle
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14291577A
Other languages
Japanese (ja)
Inventor
Mitsuo Terajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14291577A priority Critical patent/JPS5475233A/en
Publication of JPS5475233A publication Critical patent/JPS5475233A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)

Abstract

PURPOSE:To simplify the peripheral circuit of a memory by using a sequence control circuit, which varies the number of states in each cycle, to control the timing of the memory. CONSTITUTION:Memory 35 stores a program or data, and mode register 31 indicates the used mode of memory 35. Here, sequence control circuit 32 is provided which instructs the skip operation for each stage dependently upon contents set in register 31 and varies the stage in each cycle on a basis of this instruction, and further, address register 34 is provided which becomes available by the output of this circuit 32 and assignes the address of memory 35. Thus, circuit 32 which varies the number of states in each cycle is used to control the timing of memory 35, so that the peripheral circuit of memory 35 can be simplified.
JP14291577A 1977-11-29 1977-11-29 Memory controller Pending JPS5475233A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14291577A JPS5475233A (en) 1977-11-29 1977-11-29 Memory controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14291577A JPS5475233A (en) 1977-11-29 1977-11-29 Memory controller

Publications (1)

Publication Number Publication Date
JPS5475233A true JPS5475233A (en) 1979-06-15

Family

ID=15326571

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14291577A Pending JPS5475233A (en) 1977-11-29 1977-11-29 Memory controller

Country Status (1)

Country Link
JP (1) JPS5475233A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58166579A (en) * 1982-03-29 1983-10-01 Fujitsu Ltd Memory control method
JPH04230544A (en) * 1990-10-01 1992-08-19 Internatl Business Mach Corp <Ibm> Data processing apparatus for dynamically setting timing of dynamic memory system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58166579A (en) * 1982-03-29 1983-10-01 Fujitsu Ltd Memory control method
JPH04230544A (en) * 1990-10-01 1992-08-19 Internatl Business Mach Corp <Ibm> Data processing apparatus for dynamically setting timing of dynamic memory system

Similar Documents

Publication Publication Date Title
EP0126163A4 (en) Controller with status display unit.
JPS5475233A (en) Memory controller
JPS5358736A (en) Input/output control system for mos dynamic random access memory
JPS543441A (en) High-speed arithmetic system
JPS5423343A (en) Microprogram controller
JPS5769344A (en) Controller of stored program
JPS57169809A (en) Programmable logic controller
JPS5332636A (en) Ic memory
JPS5475954A (en) Data channel unit
JPS5381032A (en) Data process system
JPS5472384A (en) Sequence controller
JPS5422660A (en) Memory controller in industrial robot
JPS52127574A (en) Sequence controller with counter function
JPS5343438A (en) Locus input control circuit
JPS54530A (en) Reference control unit of memory
JPS5378740A (en) Memory control system
JPS5557905A (en) Program controller
JPS5671105A (en) Shift register type programmable controller with memory
JPS5271950A (en) Clock control system
JPS5680746A (en) Microprogram controlling device
JPS5254880A (en) Sequence controller
JPS51144137A (en) Input/output data control unit
JPS51134038A (en) Method to control input/output control unit
JPS5469937A (en) Address modifying unit
JPS5591285A (en) Paired control system