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JPS5460564A - Resin mold semiconductor device - Google Patents

Resin mold semiconductor device

Info

Publication number
JPS5460564A
JPS5460564A JP12684477A JP12684477A JPS5460564A JP S5460564 A JPS5460564 A JP S5460564A JP 12684477 A JP12684477 A JP 12684477A JP 12684477 A JP12684477 A JP 12684477A JP S5460564 A JPS5460564 A JP S5460564A
Authority
JP
Japan
Prior art keywords
chip
groove
resin
concavity
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12684477A
Other languages
Japanese (ja)
Other versions
JPS608627B2 (en
Inventor
Hisashi Yoshida
Kunihiro Tsubosaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12684477A priority Critical patent/JPS608627B2/en
Publication of JPS5460564A publication Critical patent/JPS5460564A/en
Publication of JPS608627B2 publication Critical patent/JPS608627B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE: To prevent exfoliation of the resin by providing the groove or the concavity on the upper and lower surfaces of the sealed resin substance into which the semiconductor chip is buried as if the groove or the concavity covered over the chip.
CONSTITUTION: Chip 1 is connected to lead frame 2 and buried into resin substance 3, and groove 4 and 5 are formed as if they enclosed the chip on both the upper and lower surfaces. Owing to groove 4 and 5, the stress applied to the chip is reduced to prevnet the exfoliation between the chip and resin 3. Otherwise, concavity 6 and 7 are provided instead of groove 4 and 5 in different sizes to reduce the warp of the chip and thus to facilitate easy formation of the gap to the resin
COPYRIGHT: (C)1979,JPO&Japio
JP12684477A 1977-10-24 1977-10-24 Resin mold semiconductor device Expired JPS608627B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12684477A JPS608627B2 (en) 1977-10-24 1977-10-24 Resin mold semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12684477A JPS608627B2 (en) 1977-10-24 1977-10-24 Resin mold semiconductor device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP790286A Division JPS61166052A (en) 1986-01-20 1986-01-20 Resin-molded semiconductor device

Publications (2)

Publication Number Publication Date
JPS5460564A true JPS5460564A (en) 1979-05-16
JPS608627B2 JPS608627B2 (en) 1985-03-04

Family

ID=14945261

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12684477A Expired JPS608627B2 (en) 1977-10-24 1977-10-24 Resin mold semiconductor device

Country Status (1)

Country Link
JP (1) JPS608627B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6157530U (en) * 1984-09-18 1986-04-17
US7646089B2 (en) 2008-05-15 2010-01-12 Fujitsu Limited Semiconductor package, method for manufacturing a semiconductor package, an electronic device, method for manufacturing an electronic device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6435923U (en) * 1987-08-29 1989-03-03

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6157530U (en) * 1984-09-18 1986-04-17
US7646089B2 (en) 2008-05-15 2010-01-12 Fujitsu Limited Semiconductor package, method for manufacturing a semiconductor package, an electronic device, method for manufacturing an electronic device

Also Published As

Publication number Publication date
JPS608627B2 (en) 1985-03-04

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