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JPS5453859A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5453859A
JPS5453859A JP12039777A JP12039777A JPS5453859A JP S5453859 A JPS5453859 A JP S5453859A JP 12039777 A JP12039777 A JP 12039777A JP 12039777 A JP12039777 A JP 12039777A JP S5453859 A JPS5453859 A JP S5453859A
Authority
JP
Japan
Prior art keywords
layer
entire surface
platinum
bonding parts
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12039777A
Other languages
Japanese (ja)
Inventor
Terusumi Takei
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12039777A priority Critical patent/JPS5453859A/en
Publication of JPS5453859A publication Critical patent/JPS5453859A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas

Landscapes

  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To avert electrode separation of bonding parts by letting the kinds of metals used differ with the portions from contact windows up to bonding pads and pad portions at the time of providing lead-out electrodes to semiconductor devices. CONSTITUTION:A base region 4 is diffusion-formed in a semiconductor substrate 5 which becomes a colloctor region, and an emitter region 3 is provided therein, after which a SiO2 film 1 is deposited over the entire surface. Next, contact windows for the regions 3, 4 are opened, and platinum is evaportated and is then heated, producing platinum silicide 2 in the windows. The platinum on the film 1 is etched away. Thereafter, an Al layer 7 is evaporated over the entire surface and the layer 7 is formed only on bonding parts by using a photo resist 6. The resist 6 is renewed to 11, after which a Ti layer 10, Pt layer 9, Au layer 8 are laminated and evaporated over the entire surface. Next, composite layers are left from the window inside up to one end of the Al layer 7 of the bonding parts by a lift off method.
JP12039777A 1977-10-05 1977-10-05 Semiconductor device Pending JPS5453859A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12039777A JPS5453859A (en) 1977-10-05 1977-10-05 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12039777A JPS5453859A (en) 1977-10-05 1977-10-05 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5453859A true JPS5453859A (en) 1979-04-27

Family

ID=14785188

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12039777A Pending JPS5453859A (en) 1977-10-05 1977-10-05 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5453859A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5260234A (en) * 1990-12-20 1993-11-09 Vlsi Technology, Inc. Method for bonding a lead to a die pad using an electroless plating solution

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5260234A (en) * 1990-12-20 1993-11-09 Vlsi Technology, Inc. Method for bonding a lead to a die pad using an electroless plating solution

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