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JPS54159835A - Multiple transfer instructing system - Google Patents

Multiple transfer instructing system

Info

Publication number
JPS54159835A
JPS54159835A JP6926178A JP6926178A JPS54159835A JP S54159835 A JPS54159835 A JP S54159835A JP 6926178 A JP6926178 A JP 6926178A JP 6926178 A JP6926178 A JP 6926178A JP S54159835 A JPS54159835 A JP S54159835A
Authority
JP
Japan
Prior art keywords
transfer
register
instruction
length
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6926178A
Other languages
Japanese (ja)
Inventor
Takeshi Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6926178A priority Critical patent/JPS54159835A/en
Publication of JPS54159835A publication Critical patent/JPS54159835A/en
Pending legal-status Critical Current

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  • Memory System (AREA)

Abstract

PURPOSE: To make it possible to instruct that saved data in the operating system can be transferred to a continuous area temporarily even if this data is divived into discontinuous areas in the interrupt processing of a system program.
CONSTITUTION: The number of execution times of a transfer instruction, the length of a prescribed number of discontinuous areas and the start address of these areas are added to the heading to an address table and are stored in memory 2, and an instruction register is constituted by operation code register OP, transfer length register L, transfer source address register AR and transfer destination address register BR. Then, a length and an address corresponding to contents of counter 4 which stores the number of executed transfer instructions are set to transfer length register L and transfer source address register AR, and the transfer instruction is executed to decide whether contents of counter 4 and countents of transfer instruction storage register 5 agree with each other or not. The instruction execution is finished in case of agreement, and contents of counter 4 are increased in case of disagreement.
COPYRIGHT: (C)1979,JPO&Japio
JP6926178A 1978-06-08 1978-06-08 Multiple transfer instructing system Pending JPS54159835A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6926178A JPS54159835A (en) 1978-06-08 1978-06-08 Multiple transfer instructing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6926178A JPS54159835A (en) 1978-06-08 1978-06-08 Multiple transfer instructing system

Publications (1)

Publication Number Publication Date
JPS54159835A true JPS54159835A (en) 1979-12-18

Family

ID=13397580

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6926178A Pending JPS54159835A (en) 1978-06-08 1978-06-08 Multiple transfer instructing system

Country Status (1)

Country Link
JP (1) JPS54159835A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6258367A (en) * 1985-08-20 1987-03-14 Fujitsu Ltd Data editing method for terminal search

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6258367A (en) * 1985-08-20 1987-03-14 Fujitsu Ltd Data editing method for terminal search

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