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JPS54158842A - Ultra high frequency device - Google Patents

Ultra high frequency device

Info

Publication number
JPS54158842A
JPS54158842A JP6858478A JP6858478A JPS54158842A JP S54158842 A JPS54158842 A JP S54158842A JP 6858478 A JP6858478 A JP 6858478A JP 6858478 A JP6858478 A JP 6858478A JP S54158842 A JPS54158842 A JP S54158842A
Authority
JP
Japan
Prior art keywords
dielectric
line
short
external
plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6858478A
Other languages
Japanese (ja)
Inventor
Hidetoshi Kondo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6858478A priority Critical patent/JPS54158842A/en
Publication of JPS54158842A publication Critical patent/JPS54158842A/en
Pending legal-status Critical Current

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  • Waveguide Connection Structure (AREA)

Abstract

PURPOSE: To make it possible to attain direct transmission to a low-loss line in both milli-wave and submilli-wave bands with shielding effect from an external obstacle, by equipping a semiconductor element such as a Gunn diode in a dielectric wire.
CONSTITUTION: As for the frequency multiplier, cross dielectric lines crossing at right angles on conductor plate 11 are provided with external dielectric walls 13 and 13' and movable short-plates 20 and 20', and semiconductor element 14, in stalled where dielectric lines 12 and 12' cross at right angles, is applied with a bias voltage through bias line 15. Then, impedance values of the input circuit (formed of element 14, dielectric line 12, external wall 13, and short-plate 20') and output circuit (formed of element 14, dielectric line 12', external wall 13', and short-plate 20') are adjusted respectively to extract a desirable multiplication output. Because of the abovementioned constitution, effect of shielding from the outside is given and the multiplication output can be transmitted direct via a low-loss line.
COPYRIGHT: (C)1979,JPO&Japio
JP6858478A 1978-06-06 1978-06-06 Ultra high frequency device Pending JPS54158842A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6858478A JPS54158842A (en) 1978-06-06 1978-06-06 Ultra high frequency device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6858478A JPS54158842A (en) 1978-06-06 1978-06-06 Ultra high frequency device

Publications (1)

Publication Number Publication Date
JPS54158842A true JPS54158842A (en) 1979-12-15

Family

ID=13377978

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6858478A Pending JPS54158842A (en) 1978-06-06 1978-06-06 Ultra high frequency device

Country Status (1)

Country Link
JP (1) JPS54158842A (en)

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