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JPS54146551A - Resetting system for processor - Google Patents

Resetting system for processor

Info

Publication number
JPS54146551A
JPS54146551A JP5407978A JP5407978A JPS54146551A JP S54146551 A JPS54146551 A JP S54146551A JP 5407978 A JP5407978 A JP 5407978A JP 5407978 A JP5407978 A JP 5407978A JP S54146551 A JPS54146551 A JP S54146551A
Authority
JP
Japan
Prior art keywords
reset
processor
address
start address
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5407978A
Other languages
Japanese (ja)
Other versions
JPS5826043B2 (en
Inventor
Ryozo Maeno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP53054079A priority Critical patent/JPS5826043B2/en
Publication of JPS54146551A publication Critical patent/JPS54146551A/en
Publication of JPS5826043B2 publication Critical patent/JPS5826043B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To secure a perfect isolation between the start address by the reset input given from outside and the start address in case the restart order is inserted by having the OR between the address line of the processor and the output of the FF which memorizes the reset signal.
CONSTITUTION: The OR is secured by OR circuit 3 between output Q of reset FF2 memorizing reset signal 4 and address ADRO7 of the address line of processor 1. Then FF2 is reset with the firmware to give an isolation between the start address by the reset input given from outside and the start address in case the reset is inserted. Thus, the malfunction can be avoided at the periphery of the processor.
COPYRIGHT: (C)1979,JPO&Japio
JP53054079A 1978-05-09 1978-05-09 Processor reset method Expired JPS5826043B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53054079A JPS5826043B2 (en) 1978-05-09 1978-05-09 Processor reset method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53054079A JPS5826043B2 (en) 1978-05-09 1978-05-09 Processor reset method

Publications (2)

Publication Number Publication Date
JPS54146551A true JPS54146551A (en) 1979-11-15
JPS5826043B2 JPS5826043B2 (en) 1983-05-31

Family

ID=12960599

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53054079A Expired JPS5826043B2 (en) 1978-05-09 1978-05-09 Processor reset method

Country Status (1)

Country Link
JP (1) JPS5826043B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS584418A (en) * 1981-06-30 1983-01-11 Fujitsu Ltd Resetting system of data processor
JPS6254349A (en) * 1985-09-02 1987-03-10 Nec Corp Address modification system
JPS62271113A (en) * 1986-05-20 1987-11-25 Fujitsu Ltd Microprocessor initialization control system

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60209450A (en) * 1984-04-02 1985-10-22 Mita Ind Co Ltd Copying paper cassette
JPS6277151U (en) * 1985-11-01 1987-05-18

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS584418A (en) * 1981-06-30 1983-01-11 Fujitsu Ltd Resetting system of data processor
JPS6367690B2 (en) * 1981-06-30 1988-12-27 Fujitsu Ltd
JPS6254349A (en) * 1985-09-02 1987-03-10 Nec Corp Address modification system
JPS62271113A (en) * 1986-05-20 1987-11-25 Fujitsu Ltd Microprocessor initialization control system

Also Published As

Publication number Publication date
JPS5826043B2 (en) 1983-05-31

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