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JPS54123847A - Memory transfer unit - Google Patents

Memory transfer unit

Info

Publication number
JPS54123847A
JPS54123847A JP3129678A JP3129678A JPS54123847A JP S54123847 A JPS54123847 A JP S54123847A JP 3129678 A JP3129678 A JP 3129678A JP 3129678 A JP3129678 A JP 3129678A JP S54123847 A JPS54123847 A JP S54123847A
Authority
JP
Japan
Prior art keywords
address
memory
readout
block
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3129678A
Other languages
Japanese (ja)
Inventor
Sunao Kanamori
Akira Fusaoka
Masaharu Hirayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP3129678A priority Critical patent/JPS54123847A/en
Publication of JPS54123847A publication Critical patent/JPS54123847A/en
Pending legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)
  • Indexing, Searching, Synchronizing, And The Amount Of Synchronization Travel Of Record Carriers (AREA)

Abstract

PURPOSE:To enable readout and write-in form the rotary type memory without waiting time immediately, by providing the operation circuit calculating the memory address after trnasfer corresponding to the head address before transfer and the auxiliary memory memorizing the result. CONSTITUTION:The first and second auxiliary memories 5,6 are provided, and the operation circuit 7 is added to the control section 3. The content which has been address 0 at the write-in before is written in the address c in the block I of the rotary type first memory 1, and when the block I is designated from the control section 3, readout is immediately made without waiting the address coming beneath the magnetic head, and the block J of the second memory 2 performs write-in from the address 0 corresponding to the readout start address a at this time. Accordingly, since the head address c before transfer corresponds to the address d after transfer, the equation d=c-a is operated 7(the memory content of the address i of the memory 5 is used as c.) and the memory content is renewed by giving the result of operation d to the address j of the memory 6, allowing to provide the readout from the next block J.
JP3129678A 1978-03-17 1978-03-17 Memory transfer unit Pending JPS54123847A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3129678A JPS54123847A (en) 1978-03-17 1978-03-17 Memory transfer unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3129678A JPS54123847A (en) 1978-03-17 1978-03-17 Memory transfer unit

Publications (1)

Publication Number Publication Date
JPS54123847A true JPS54123847A (en) 1979-09-26

Family

ID=12327325

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3129678A Pending JPS54123847A (en) 1978-03-17 1978-03-17 Memory transfer unit

Country Status (1)

Country Link
JP (1) JPS54123847A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6234256A (en) * 1985-08-07 1987-02-14 Alps Electric Co Ltd Disk cache device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6234256A (en) * 1985-08-07 1987-02-14 Alps Electric Co Ltd Disk cache device

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