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JPS54104785A - P-wel and its forming method - Google Patents

P-wel and its forming method

Info

Publication number
JPS54104785A
JPS54104785A JP1169678A JP1169678A JPS54104785A JP S54104785 A JPS54104785 A JP S54104785A JP 1169678 A JP1169678 A JP 1169678A JP 1169678 A JP1169678 A JP 1169678A JP S54104785 A JPS54104785 A JP S54104785A
Authority
JP
Japan
Prior art keywords
type
substrate
well region
layer
impurity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1169678A
Other languages
Japanese (ja)
Inventor
Toshiaki Ogata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP1169678A priority Critical patent/JPS54104785A/en
Publication of JPS54104785A publication Critical patent/JPS54104785A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/858—Complementary IGFETs, e.g. CMOS comprising a P-type well but not an N-type well

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To increase the degree of integration, by providing the layer of higher impurity concentration than the substrate at surrounding of the well region, when constituting C-MOSIC by forming the P channel region on the semiconductor substrate and by forming N channel region in the P<-> type well region. CONSTITUTION:The P<-> type well region 5 is formed by implanting B ions being P type impurity in the N type Si substrate through the use of a given mask. The P ions being N type impurity are injected by using the mask extending the injection part with the mask used in this case or side etching. After that, the impurity of N and P type is simultaneously diffused with heat treatment, forming the N type layer 6 higher in impurity concentration than the substrate 1 at the surrounding of the well region by taking faster diffusion speed of P than B. Further, the P channel element 3 is formed in the substrate 1 and the N channel element 4 is formed in the well region 5. Thus, the spread of the depletion layer in the layer 6 is made small and the distance between the two channels can be reduced.
JP1169678A 1978-02-03 1978-02-03 P-wel and its forming method Pending JPS54104785A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1169678A JPS54104785A (en) 1978-02-03 1978-02-03 P-wel and its forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1169678A JPS54104785A (en) 1978-02-03 1978-02-03 P-wel and its forming method

Publications (1)

Publication Number Publication Date
JPS54104785A true JPS54104785A (en) 1979-08-17

Family

ID=11785189

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1169678A Pending JPS54104785A (en) 1978-02-03 1978-02-03 P-wel and its forming method

Country Status (1)

Country Link
JP (1) JPS54104785A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS586162A (en) * 1981-07-02 1983-01-13 Seiko Epson Corp semiconductor equipment
JPS63128659A (en) * 1986-11-18 1988-06-01 Seiko Epson Corp semiconductor equipment

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS586162A (en) * 1981-07-02 1983-01-13 Seiko Epson Corp semiconductor equipment
JPS63128659A (en) * 1986-11-18 1988-06-01 Seiko Epson Corp semiconductor equipment

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