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JPS54100270A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS54100270A
JPS54100270A JP621978A JP621978A JPS54100270A JP S54100270 A JPS54100270 A JP S54100270A JP 621978 A JP621978 A JP 621978A JP 621978 A JP621978 A JP 621978A JP S54100270 A JPS54100270 A JP S54100270A
Authority
JP
Japan
Prior art keywords
region
type
layer
coated
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP621978A
Other languages
Japanese (ja)
Inventor
Tadao Kachi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP621978A priority Critical patent/JPS54100270A/en
Publication of JPS54100270A publication Critical patent/JPS54100270A/en
Pending legal-status Critical Current

Links

Landscapes

  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE: To reduce the distance of the depletion layer necessary for the pinch-off state and then to lower the active voltage of the electrostatic conduction transistor by providing previously the conducting region opposite to the source region right under the source region.
CONSTITUTION: N+-buried layer 18 to be the drain region later is formed on P-type Si substrate, and N- layer 17 is epitaxial-grown on the enrire surface. SiO2 film 14 is then coated on the entire surface with the opening drilled to form ring-shaped P-type region 15 plus P-type region 19 positioning at the center of region 15. After this, N-type source region 16 is formed through diffusion covering over the entire surface of region 19. In this case, the lateral extensive width is set equal between region 16 and 19 with difference x3 of the widths set to nearly zero. In case it is hard to secure x3 set to zero due to the dispersion of the manufacturing processes, the width of region 19 is set smaller than that of region 16. Then electrode 11 and 12 are attached to region 16 and 15 each, and electrode 13 is coated on layer 18.
COPYRIGHT: (C)1979,JPO&Japio
JP621978A 1978-01-25 1978-01-25 Semiconductor device Pending JPS54100270A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP621978A JPS54100270A (en) 1978-01-25 1978-01-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP621978A JPS54100270A (en) 1978-01-25 1978-01-25 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS54100270A true JPS54100270A (en) 1979-08-07

Family

ID=11632401

Family Applications (1)

Application Number Title Priority Date Filing Date
JP621978A Pending JPS54100270A (en) 1978-01-25 1978-01-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS54100270A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63269578A (en) * 1987-04-28 1988-11-07 Olympus Optical Co Ltd semiconductor equipment
JP2014229859A (en) * 2013-05-27 2014-12-08 ルネサスエレクトロニクス株式会社 VERTICAL CHANNEL JUNCTION SiC POWER FET AND METHOD FOR MANUFACTURING THE SAME

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50120780A (en) * 1974-03-08 1975-09-22

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50120780A (en) * 1974-03-08 1975-09-22

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63269578A (en) * 1987-04-28 1988-11-07 Olympus Optical Co Ltd semiconductor equipment
JP2014229859A (en) * 2013-05-27 2014-12-08 ルネサスエレクトロニクス株式会社 VERTICAL CHANNEL JUNCTION SiC POWER FET AND METHOD FOR MANUFACTURING THE SAME

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