JPH1168159A - Group-iii nitride semiconductor element and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a group-III semiconductor element of a quantum well structure which can prevent the sublimation of a well layer at the time of forming a barrier layer therein, and can control its film thickness with good crystallinity and enhance luminous efficiency. SOLUTION: N2 or H2 gas is supplied at a flow rate of 20 liters/min, an NH3 gas is supplied at a flow rate of 10 liters/min and a TMG is supplied at a flow rate of 2.0×10<-4> mol./min at a substrate temperature of 900 deg.C. to form a barrier layer 51 of GaN having a thickness of about 35 Å. Next, the substrate temperature is reduced down to 600 deg.C, and the supply amount of H2 or NH3 is made constant, under which condition TMG is supplied at a flow rate of 7.2×10<-5> mol./min and TMI is supplied at a flow rate of 0.19×10<-4> mol./min to form a well layer 52 of In0.20 Ga0.80 N having a thickness of about 35 Å. Subsequently, the substrate temperature is kept at 600 deg.C, N2 or H2 is supplied at a flow rate of 20 lit./min, NH3 is supplied at a flow rate of 10 lit./min, and TMG is supplied at a flow rate of 2.0×10<-4> mol./min to form a cap layer 53. (a) Then the substrate temperature is increased from 600 deg.C to 900 deg.C, during which the cap layer 53 disappears due to pyrolysis reaction. (b) When the substrate temperature reaches 900 deg.C, the next barrier layer 51 is formed on the well layer 52 under these conditions.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to the group III nitride semiconductor, for example, a method of manufacturing a device comprising a _{Al X Ga Y In 1-XY} N. In particular, the present invention relates to a method for manufacturing a device having a quantum well structure in which a well layer and a barrier layer are stacked.

[0002]

2. Description of the Related Art Conventionally, in a group III nitride semiconductor, as a light emitting layer of a light emitting diode and an active layer of a semiconductor laser,
There is a technique in which a light emission intensity is improved by using a quantum well structure including a well layer and a barrier layer having a wider band gap than the well layer. For example, a well layer made of Ga _0.57 In _0.43 N
A device with a single quantum well (SQW) structure sandwiched between barrier layers consisting of _0.95 In _0.05 N and Al _0.1 Ga _0.9 N (JAPANESE JOUR
NAL OF APPLIED PHYSICS (JJAP), Vol. 34 (1995) pp. L797-L
799) and a well layer consisting of Ga _0.8 In _0.2 N and Ga _0.95 In _0.05 N
Having a multiple quantum well (MQW) structure in which a barrier layer composed of a plurality of layers is stacked at a predetermined period (JJAP, Vol. 35 (1996) pp. L)
74-L76) are known. The growth temperature in the production of these group III nitride semiconductors is that of a well layer <a barrier layer. In order to improve the luminous efficiency, it is important to control the crystallinity of each layer constituting the quantum well structure and the thickness of each layer. Factor.

[0003]

However, in the above prior art, in the temperature raising process for growing the barrier layer after the growth of the well layer, a part of the well layer is sublimated by thermal decomposition to grow the barrier layer. In some cases, the well layer becomes thinner than the initial thickness. In addition, there is a problem that the crystallinity of the well layer surface is deteriorated by the sublimation. In addition, a portion having a non-uniform composition due to evaporation of In is formed in a part of the well layer in the plane. In addition, if the temperature rise time varies, as a result, in the case of the quantum well structure, particularly in the case of the MQW structure, the thickness of each well layer becomes non-uniform, and the luminous efficiency decreases due to the formation of non-uniform quantum levels. There is a problem such as generation of an unnecessary emission center.

Accordingly, it is an object of the present invention to prevent sublimation of a well layer when growing a barrier layer,
It is an object to prevent generation of unnecessary light emission centers and improve light emission efficiency.

[0005]

According to the first aspect of the present invention, there is provided a semiconductor device having at least one cycle of a stacked structure of a well layer and a barrier layer made of a group III nitride semiconductor. In the method of manufacturing a group III nitride semiconductor device having a quantum well structure, after formation of a well layer, a cap layer having a band gap wider than that of the well layer near the formation temperature of the well layer and having the same or smaller band gap as the barrier layer After that, the cap layer is removed by thermal decomposition in the process of raising the temperature to the temperature at the time of forming the barrier layer, and the barrier layer is formed on the well layer. Thereby, when forming the barrier layer, the sublimation of the well layer can be prevented and the barrier layer can be formed on the well layer. Therefore, the thickness of each well layer becomes uniform, and good crystallinity can be maintained. As a result, generation of unnecessary light emission centers can be prevented, and light emission efficiency can be improved.

Preferably, the well layer is formed of Al _X1 Ga _Y1 In _1-X1-Y1 N (0 ≦ X1 ≦ 1,0 ≦ Y1 ≦ 1,
0 ≦ X1 + Y1 ≦ 1), and the barrier layer is Al _X2 Ga _Y2 In _1-X2-Y2 N
(0 ≦ X2 ≦ 1,0 ≦ Y2 ≦ 1, 0 ≦ X2 + Y2 ≦ 1), and the cap layer is made of Al _X3 Ga _Y3 In _1-X3-Y3 N (0 ≦ X3 ≦ 1,0 ≦ Y3 ≦ 1, 0 ≦ X3 + Y3
≦ 1). Further, as in the means according to claim 3, the well layer is composed of Ga _X4 In _1-X4 N (0 ≦ X4 ≦ 1), and the barrier layer is Al _X2 Ga _Y2 In _1-X2-Y2 N (0 ≦ X2 ≦ 1,0 ≦ Y2 ≦ 1,0 ≦ X2
+ Y2 ≦ 1), the well layer is made of Ga _X5 In _1-X5 N (0 ≦ X5 <1), and the barrier layer is made of Al _X6 Ga _1-X6. N (0 ≦ X6 ≦ 1), and the cap layer is made of Al
_{X7Ga1 -X7N} (0≤X7≤1, X7≤X6)
The well layer is made of Ga _X5 In _1-X5 N (0 ≦ X5 <1)
, The barrier layer is composed of Al _X6 Ga _1-X6 N (0 ≦ X6 ≦ 1), and the cap layer is composed of Ga _X8 In _1-X8 N (0 <X8 ≦ 1, X5 <X8) The well layer is made of Ga _X9.
In _1-X9 N (0 <X9 <1), and barrier layer and cap layer are G
By using aN, better effects can be obtained.

[0007] According to the means of the present invention, by setting the thickness of the cap layer to a thickness that can be eliminated at the start of the barrier layer formation when the temperature rise to the formation temperature of the barrier layer is completed. The thickness of the layer can be made uniform with higher accuracy.
According to the means of claim 8, since the growth rate of the cap layer is set to 10 ° / min or more, a light emitting layer (well layer) having a good crystal state can be obtained, so that the light emitting output is weak or the light emitting layer has a low light emitting layer. There is no unevenness in light emission. The reason why the growth rate is set to 10 ° / min or more is that the light emitting layer is unstable in crystal structure due to the fact that In is easily sublimated even at the crystal growth temperature of the cap layer. This is because it is necessary to cover with a cap layer. This growth condition is desirable for blue light emission. According to the means of claim 9, the growth rate of the cap layer is 15 ° / min or more and 30 ° / min.
/ Min or less, a light-emitting layer (well layer) with a good crystalline state can be obtained, so that the light-emission output is not weak and the light-emission of the light-emitting layer is not uneven. 15 growth rate
The reason why the rate is set to 発 光 / min or more is that the light emitting layer is unstable in crystal structure because of the fact that In easily sublimates even under the crystal growth temperature of the cap layer. It is necessary to cover with. Further, when the growth rate of the cap layer is 30 ° / min or more, the crystal growth rate of the cap layer is too high, so that the cap layer is difficult to grow uniformly, and the thickness or structure of the cap layer is likely to be uneven. Non-uniformity also occurs in the layer thermal decomposition state, which causes spatial unevenness in the light-emitting layer of the emission intensity and causes undesired unevenness in the emission wavelength in terms of color. Therefore, the growth rate of the cap layer is desirably 30 ° / min or less. This growth condition is desirable for green emission. The reason why the condition for the crystal growth rate of the cap layer is more strict in the case of manufacturing a green LED than in the case of manufacturing a blue LED is that the green LE
This is because the D well layer has a larger indium (In) composition ratio and is therefore more unstable in crystal structure.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described based on specific embodiments. FIG. 1 is a schematic cross-sectional configuration diagram of a light emitting device 10 formed of a group III nitride semiconductor formed on a sapphire substrate 1. A buffer layer 2 made of aluminum nitride (AlN) having a thickness of about 25 nm is provided on a substrate 1, and a high carrier concentration layer 3 made of silicon (Si) doped with GaN having a thickness of about 4.0 μm is provided thereon. Is formed.

Then, a film having a thickness of about
35 ° GaN barrier layer 51 and about 35 mm thick In _0.20
MQ in which well layers 52 of Ga _0.80 N are alternately stacked
A light emitting layer 5 having a W structure is formed. The barrier layer 51 is 6
The layers and well layers 52 are composed of five layers. On the light emitting layer 5, a cladding layer 6 of p-type Al _0.15 Ga _0.85 N having a thickness of about 50 nm is formed. Further, a contact layer 7 of p-type GaN having a thickness of about 100 nm is formed on the cladding layer 6.

A light-transmitting electrode 9 is formed on the contact layer 7 by metal evaporation, and an electrode 8 is formed on the high carrier concentration layer 3.
Are formed. The light-transmitting electrode 9 is
It is composed of cobalt (Co) having a thickness of about 40 ° and a gold (Au) having a thickness of about 60 ° and being bonded to the Co. The electrode 8 is made of vanadium (V) having a thickness of about 200 ° and aluminum (Al) or an Al alloy having a thickness of about 1.8 μm.

Next, a method for manufacturing the light emitting device 10 will be described. The light emitting device 10 was manufactured by vapor phase growth by metal organic chemical vapor deposition (hereinafter abbreviated as “MOVPE”). The gases used were ammonia (NH ₃ ), carrier gas (H ₂ , N ₂ ), trimethylgallium (Ga (CH ₃ ) ₃ ) (hereinafter referred to as “TMG”), and trimethylaluminum (Al (CH ₃ )).
₃ ) (hereinafter referred to as “TMA”), trimethylindium (In
(CH ₃ ) ₃ ) (hereinafter referred to as “TMI”), silane (SiH ₄ ) and cyclopentadienyl magnesium (Mg (C ₅ H ₅ ) ₂ ) (hereinafter “CP
₂ Mg ”).

First, a single-crystal substrate 1 whose main surface is the a-plane cleaned by organic cleaning and heat treatment is mounted on a susceptor placed in a reaction chamber of a MOVPE apparatus. Next, H ₂ at normal pressure
At a flow rate of 2 liter / min for about 30 minutes while
The substrate 1 was baked at 00 ° C. Then, by lowering the temperature to 400 ° C., the H ₂ 20liter / min and NH ₃ 10liter / min, TM
A was supplied at 1.8 × 10 ⁻⁵ mol / min to form a buffer layer 2 of AlN having a thickness of about 25 nm. Next, the temperature of the substrate 1 was maintained at 1150 ° C., H ₂ was 20 liter / min, and NH ₃ was 10 liter / min.
Min, TMG 1.7 × 10 ^-4 mol / min, 0.86 ppm by H ₂ gas
Silane diluted at 20 × 10 ^-8 mol / min, the film thickness is about 4.0 μm, the electron concentration is 2 × 10 ¹⁸ / cm ³ , and the Si concentration is 4 × 10 ¹⁸ / c
A high carrier concentration layer 3 made of m ³ GaN was formed.

After forming the high carrier concentration layer 3 described above,
The light emitting layer 5 having the MQW structure was formed by a method schematically shown in FIG. First, the temperature of the substrate 1 is set to 900 ° C. and N ₂ or H ₂
Was supplied at a rate of 20 liter / min, NH ₃ was supplied at a rate of 10 liter / min, and TMG was supplied at a rate of 2.0 × 10 ⁻⁴ mol / min to form a GaN barrier layer 51 having a thickness of about 35 °. Next, the temperature of the substrate 1 was lowered to 600 ° C., and the supply amount of N _2, H ₂ , and NH _{3 was} kept constant, and TMG was changed to 7.
The well layer 52 of In _0.20 Ga _0.80 N having a thickness of about 35 ° was formed by supplying 2 × 10 ⁻⁵ mol / min and TMI at 0.19 × 10 ⁻⁴ mol / min. Next, the temperature of the substrate 1 was maintained at 600 ° C., N ₂ or H ₂ was 20 liter / min, NH ₃ was 10 liter / min, and TMG was 2.0 × 10 2
^{At a rate of -4} mol / min, a cap layer 53 made of GaN having a thickness of about 35 ° was formed (see FIG. 2A). Then, the temperature of the substrate 1 is increased from 600 ° C. to 900 ° C. In the course of this temperature rise, the cap layer 53 disappears due to thermal decomposition (FIG. 2).
(B)). When the temperature of the substrate 1 reaches 900 ° C,
The next barrier layer 51 was formed on the well layer 52 under the above conditions (fifth step, see FIG. 2C). According to the method shown in FIG. 2, the barrier layer 51 and the well layer 52 are formed in five periods,
A barrier layer 51 made of GaN was formed thereon. Thus, the light emitting layer 5 having the MQW structure having five periods was formed.

[0014] Then, maintaining the temperature of the substrate 1 to 1100 ° C., N ₂
Or H ₂ 10liter / min and NH ₃ 10liter / min, 1.0 × the TMG
10 ^-4 mol / min, TMA 1.0 × 10 ^-4 mol / min, CP ₂ Mg 2
X 10 ^-5 mol / min, film thickness about 50 nm, concentration 5 x 10 ¹⁹
/ cm ³ p-type Al _0.15 Ga _0.85 doped with magnesium (Mg)
A cladding layer 6 made of N was formed. Next, the temperature of the substrate 1 was maintained at 1100 ° C., N ₂ or H ₂ was 20 liter / min, and NH ₃ was 10 liter / min.
liter / min, TMG 1.12 × 10 ^-4 mol / min, CP ₂ Mg 2 × 10
^-5 mol / min, supplied at a film thickness of about 100 nm and a concentration of 5 × 10 ¹⁹ / c
A contact layer 7 made of p-type GaN doped with m ³ Mg was formed.

Next, an etching mask is formed on the contact layer 7, the etching mask in a predetermined region is removed, and the portions of the contact layer 7, the cladding layer 6, the light emitting layer 5 and the high portions not covered with the etching mask are removed. A part of the carrier concentration layer 3 was etched by reactive ion etching using a gas containing chlorine to expose the surface of the high carrier concentration layer 3. Next, with the etching mask left, a photoresist is applied to the entire surface, a window is formed in a predetermined region on the exposed surface of the high carrier concentration layer 3 by photolithography, and a high vacuum of the order of 10 ⁻⁶ Torr or less is formed. After exhausting, the film thickness
200 mm of vanadium (V) and about 1.8 μm thick Al are deposited. Thereafter, the photoresist and the etching mask are removed.

Subsequently, a photoresist is applied on the surface, and the phytoresist of the electrode forming portion on the contact layer 7 is removed by photolithography to form a window, and the contact layer 7 is exposed. After evacuating the exposed contact layer 7 to a high vacuum of the order of 10 ^-6 Torr or less, Co is deposited to a thickness of about 40 °, and Au is deposited to a thickness of about 60 ° on the Co. Next, the sample was taken out of the vapor deposition apparatus, and Co and Au deposited on the photoresist by a lift-off method were removed,
A translucent electrode 9 for the contact layer 7 is formed.

Thereafter, the sample atmosphere is evacuated by a vacuum pump, and O ₂ gas is supplied to a pressure of 3 Pa. At that time, the atmosphere temperature is set to about 550 ° C., and heating is performed for about 3 minutes. The p-type resistance of the layer 6 was reduced, and the alloying treatment of the contact layer 7 and the electrode 9 and the alloying treatment of the high carrier concentration layer 3 and the electrode 8 were performed. Thus, an electrode 8 for the high carrier concentration layer 3 and an electrode 9 for the contact layer 7 were formed.

As described above, by forming the cap layer 53 on the well layer 52 and then forming the barrier layer 51, the cap layer 53 is thermally decomposed and removed during the temperature rise. Since the layer 52 is not damaged, a uniform film thickness can be formed without deteriorating the crystallinity of each well layer 52. Thereby, generation of unnecessary light emission centers can be prevented, and light emission efficiency can be improved.

With respect to the blue LED, a number of samples with various growth rates of the cap layer 53 were prepared, and the emission output was measured. The result is shown in FIG. As can be seen from FIG. 3, when the crystal growth rate of the cap layer is 10 ° / min or more, a light emitting layer (well layer) having a good crystalline state can be obtained. , And a desirable LED can be manufactured. More preferably, the crystal growth rate of the cap layer is set to 1
If it is 2 ° / min or more, the highest light emission output can be obtained.
Also, for the green LED, a number of samples with various growth rates of the cap layer 53 were prepared, and the luminescence output was measured. FIG. 4 shows the results. As can be seen from FIG. 4, when the crystal growth rate of the cap layer is set to 15 to 30 ° / min, a light emitting layer (well layer) having a good crystal state can be obtained, so that the light emitting output is weak or the light emitting layer emits light. A desirable LED can be manufactured without causing unevenness. More preferably, the crystal growth rate of the cap layer is set at 20.
When the angle is set to Å25 ° / min, the highest light emission output is obtained.
For example, in the above embodiment, in order to make the crystal growth rate of the cap layer 10 to 30 ° / min, the temperature of the substrate 1 is maintained at 600 ° C. after the well layer 52 is formed, and N ₂ or H ₂ is reduced to 15 ° C.
～23Liter / min, the NH ₃ 8~12liter / min, 8 × the TMG
It may be supplied at a rate of 10 ^{−6 to} 2.4 × 10 ⁻⁵ mol / min.

In this embodiment, the composition of the barrier layer 51 is GaN, but Al _X2 Ga _Y2 In _1-X2-Y2 N (0 ≦ X2 ≦ 1,0 ≦ Y2 ≦ 1,0 ≦ X2
+ Y2 ≦ 1). The composition of the well layer 52 was In _0.20 Ga _0.80 N, but Al _X1 Ga _Y1 In _1-X1-Y1 N (0 ≦ X1
≦ 1,0 ≦ Y1 ≦ 1, 0 ≦ X1 + Y1 ≦ 1). For example, the well layer 52 is composed of Ga _X4 In _1-X4 N (0 ≦ X4 ≦ 1),
The barrier layer 51 is formed of Al _X2 Ga _Y2 In _1-X2-Y2 N (0 ≦ X2 ≦ 1,0 ≦ Y2 ≦
1, 0 ≦ X2 + Y2 ≦ 1). Also, the cap layer 5
3 was GaN, but Al _X3 Ga _Y3 In _1-X3-Y3 N (0 ≦ X3 ≦
It suffices that 1,0 ≦ Y3 ≦ 1,0 ≦ X3 + Y3 ≦ 1) is satisfied. For example, the well layer 52 is composed of Ga _X5 In _1-X5 N (0 ≦ X5 <1), the barrier layer 51 is composed of Al _X6 Ga _1-X6 N (0 ≦ X6 ≦ 1), and the cap layer 53 is It may be composed of Al _X7 Ga _1-X7 N (0 ≦ X7 ≦ 1, X7 ≦ X6). Further, the well layer 52 is composed of Ga _X5 In _1-X5 N (0 ≦ X5 <1), the barrier layer 51 is composed of Al _X6 Ga _1-X6 N (0 ≦ X6 ≦ 1),
The cap layer 53 may be composed of Ga _X8 In _1-X8 N (0 <X8 ≦ 1, X5 <X8), and the well layer 52 is composed of Ga _X9 In _1-X9 N (0 <X9 <1). Alternatively, the barrier layer 51 and the cap layer 53 may be made of GaN. Further, in this embodiment, the thickness of the cap layer 53 is such that it disappears due to thermal decomposition during the process of raising the temperature. In this case, after the temperature reaches the barrier layer 51 formation temperature, the temperature may be maintained until the cap layer 53 disappears. In this embodiment, the light emitting layer 5 of the light emitting element 10 is used.
Is an MQW structure, but may be an SQW structure. In this embodiment, the temperature at the time of forming the cap layer 53 is
Although the temperature was set to 600 ° C., which is the same as the formation temperature, the film may be formed in the range of 600 to 650 ° C. In addition, the present invention can be applied to light emitting elements such as LEDs and LDs and light receiving elements.

[Brief description of the drawings]

FIG. 1 is a schematic view showing a configuration of a light emitting device obtained by using a method of manufacturing a GaN-based compound semiconductor according to a specific example of the present invention.

FIG. 2 is a schematic view illustrating a method for manufacturing a GaN-based compound semiconductor according to a specific example of the present invention.

FIG. 3 is a graph showing a measurement result of a light emission output measured by changing a crystal growth rate of a cap layer of a semiconductor light emitting device for a blue LED prototyped by applying the present invention.

FIG. 4 is a graph showing a measurement result of a light emission output measured by changing a crystal growth rate of a cap layer of a green LED semiconductor light emitting device prototyped by applying the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Sapphire substrate 2 Buffer layer 3 High carrier concentration layer 5 Light emitting layer 51 Barrier layer 52 Well layer 53 Cap layer 6 Cladding layer 7 Contact layer 8 Electrode 9 Translucent electrode 10 Light emitting element

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shinya Asami 1 Ochiai Nagahata, Kasuga-cho, Nishi-Kasugai-gun, Aichi Prefecture Inside Toyoda Gosei Co., Ltd. Inside Toyoda Gosei Co., Ltd. (72) Inventor Katsuhisa Sawazaki 1 Ochiai Nagahata, Kasuga-machi, Nishi-Kasugai-gun, Aichi Prefecture Inside Toyoda Gosei Co., Ltd. Inside the corporation

Claims (9)

[Claims] 1. A method of manufacturing a Group III nitride semiconductor having a quantum well structure having at least one cycle of a stacked structure of a well layer made of a Group III nitride semiconductor and a barrier layer, the method comprising: Forming a cap layer having a band gap wider than that of the well layer near the formation temperature of the well layer and having the same or narrower band gap as the barrier layer, and then increasing heat to a temperature at the time of formation of the barrier layer. A method for manufacturing a group III nitride semiconductor device, comprising: removing the cap layer by decomposition to form the barrier layer on the well layer. 2. The method according to claim 1, wherein the well layer is formed of Al _X1 Ga _Y1 In _1-X1-Y1 N (0 ≦ X1
≦ 1,0 ≦ Y1 ≦ 1,0 ≦ X1 + Y1 ≦ 1), wherein the barrier layer is A
l _X2 Ga _Y2 In _1-X2-Y2 N (0 ≦ X2 ≦ 1,0 ≦ Y2 ≦ 1,0 ≦ X2 + Y2 ≦ 1), and the cap layer is Al _X3 Ga _Y3 In _1-X3-Y3 N (0 ≦ X3 ≦
2. The method for manufacturing a group III nitride semiconductor device according to claim 1, wherein the method comprises: 1,0 ≦ Y3 ≦ 1,0 ≦ X3 + Y3 ≦ 1). The well layer is made of Ga _X4 In _1-X4 N (0 ≦ X4 ≦ 1), and the barrier layer is made of Al _X2 Ga _Y2 In _1-X2-Y2 N (0 ≦ X2 ≦ 1,
3. The method of claim 2, wherein 0 ≦ Y2 ≦ 1, 0 ≦ X2 + Y2 ≦ 1). 4. The method according to claim 1, wherein the well layer is made of Ga _X5 In _{1 -X5} N (0 ≦ X5 <1), the barrier layer is made of Al _X6 Ga _{1 -X6} N (0 ≦ X6 ≦ 1), and the cap layer is Is Al _X7 Ga _1-X7 N (0 ≦ X7 ≦ 1, X7 ≦ X6)
3. The method for manufacturing a group III nitride semiconductor device according to claim 2, comprising: 5. The well layer is made of Ga _X5 In _1-X5 N (0 ≦ X5 <1), the barrier layer is made of Al _X6 Ga _1-X6 N (0 ≦ X6 ≦ 1), and the cap layer is Is Ga _X8 In _1-X8 N (0 <X8 ≦ 1, X5 <X8)
3. The method for manufacturing a group III nitride semiconductor device according to claim 2, comprising: 6. The group 3 according to claim 2, wherein said well layer is made of Ga _X9 In _1-X9 N (0 <X9 <1), and said barrier layer and said cap layer are made of GaN. A method for producing a nitride semiconductor substrate. 7. The method according to claim 1, wherein the thickness of the cap layer is a thickness that can be eliminated at the start of the formation of the barrier layer after the temperature rise to the formation temperature of the barrier layer is completed. 7. The method for manufacturing a group III nitride semiconductor device according to any one of the above items 6. 8. The crystal growth rate of the cap layer is 10
The method of manufacturing a group III nitride semiconductor device according to any one of claims 1 to 7, wherein the rate is Å / min or more. 9. The crystal growth rate of the cap layer is 15
The method for manufacturing a Group III nitride semiconductor device according to any one of claims 1 to 8, wherein the temperature is not less than Å / min and not more than 30 ° / min.