JPH1168005A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH1168005A JPH1168005A JP22476397A JP22476397A JPH1168005A JP H1168005 A JPH1168005 A JP H1168005A JP 22476397 A JP22476397 A JP 22476397A JP 22476397 A JP22476397 A JP 22476397A JP H1168005 A JPH1168005 A JP H1168005A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- semiconductor device
- sealing resin
- semiconductor element
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 119
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000011347 resin Substances 0.000 claims abstract description 70
- 229920005989 resin Polymers 0.000 claims abstract description 70
- 238000007789 sealing Methods 0.000 claims abstract description 63
- 239000000126 substance Substances 0.000 claims description 10
- 239000004020 conductor Substances 0.000 claims description 6
- 239000000853 adhesive Substances 0.000 claims description 5
- 230000001070 adhesive effect Effects 0.000 claims description 5
- 230000005855 radiation Effects 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 230000001678 irradiating effect Effects 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 3
- 238000013461 design Methods 0.000 abstract description 2
- 229910000679 solder Inorganic materials 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 238000012360 testing method Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 239000005022 packaging material Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置、特に
リードフレームを用いた樹脂封止型半導体装置のパッケ
ージ構造と、その製造方法に関するものである。The present invention relates to a semiconductor device, and more particularly to a package structure of a resin-sealed semiconductor device using a lead frame and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】図７は、リードフレームを用いた従来の
一般的な樹脂封止型半導体装置を示す断面図である。図
において、１は封止樹脂、２はＩＣ集積回路、３はリー
ドフレーム、３ｃは外部リード、４はＩＣ集積回路２と
リードフレーム３を電気的に接続するワイヤで、例えば
金線、６は半導体装置を実装する回路基板、７は回路基
板６の電極部、８は外部リード３ｃと回路基板６の電極
部７とを接続する導電性物質で、例えばはんだペースト
である。このように、従来より広く使用されているリー
ドフレーム３を用いた樹脂封止型半導体装置は、封止樹
脂１から導出されたリードフレーム３の外部リード３ｃ
をはんだ付けにより回路基板６に実装していた。その際
に必要な面積は、封止樹脂１部よりも１〜２割程度も大
きく、外部リードによる接続を行わないＢＧＡ（ボール
グリッドアレイ）等の高密度実装型半導体装置と比べて
１. ５〜３倍程度の実装面積が必要であった。2. Description of the Related Art FIG. 7 is a sectional view showing a conventional general resin-encapsulated semiconductor device using a lead frame. In the figure, 1 is a sealing resin, 2 is an IC integrated circuit, 3 is a lead frame, 3c is an external lead, 4 is a wire for electrically connecting the IC integrated circuit 2 and the lead frame 3, for example, a gold wire, 6 is A circuit board on which the semiconductor device is mounted, 7 is an electrode portion of the circuit board 6, and 8 is a conductive material for connecting the external lead 3c and the electrode portion 7 of the circuit board 6, for example, a solder paste. As described above, the resin-encapsulated semiconductor device using the lead frame 3, which has been widely used in the related art, includes the external leads 3 c of the lead frame 3 derived from the sealing resin 1.
Was mounted on the circuit board 6 by soldering. The area required at this time is about 10 to 20% larger than one part of the sealing resin, and is 1.5 times larger than that of a high-density mounting type semiconductor device such as a BGA (ball grid array) which is not connected by external leads. Approximately three times the mounting area was required.
【０００３】一方、特開平１−１２８８９２号公報で提
案された半導体装置のように、リードフレームの底面の
一部を封止樹脂より露出させて回路基板と接続するよう
に構成された半導体装置では、外部リード３ｃを有する
従来の一般的な半導体装置に比べて実装面積の縮小が可
能である。図８は、特開平１−１２８８９２号公報で提
案された半導体装置を示す断面図であり、図において１
は成形樹脂、２はＩＣチップ、１１はチップ搭載片、１
２は端子、１３は半田バンプを示す。本例では、リード
フレーム３の複数本の各リードに形成されたチップ搭載
片１１に、ＩＣチップ２の電極形成面を下向きにして搭
載し、チップ搭載片１１とＩＣチップ２の電極を半田バ
ンプ１３で接合し、チップ搭載片１１の裏面を成形樹脂
１の下側表面から露出させ、外部接続用の端子１２とし
たものである。On the other hand, as in a semiconductor device proposed in Japanese Patent Application Laid-Open No. 1-128892, a semiconductor device in which a part of the bottom surface of a lead frame is exposed from a sealing resin and connected to a circuit board is disclosed. The mounting area can be reduced as compared with a conventional general semiconductor device having the external leads 3c. FIG. 8 is a sectional view showing a semiconductor device proposed in Japanese Patent Application Laid-Open No. 1-128892.
Is a molding resin, 2 is an IC chip, 11 is a chip mounting piece, 1
2 indicates a terminal, and 13 indicates a solder bump. In this example, the IC chip 2 is mounted on the chip mounting piece 11 formed on each of the plurality of leads of the lead frame 3 with the electrode formation surface of the chip mounting face down, and the chip mounting piece 11 and the electrode of the IC chip 2 are solder bumped. 13, the back surface of the chip mounting piece 11 is exposed from the lower surface of the molding resin 1 to form a terminal 12 for external connection.
【０００４】[0004]
【発明が解決しようとする課題】このように、従来のリ
ードフレーム３を用いた樹脂封止型半導体装置は、封止
樹脂１から導出された外部リード３ｃを回路基板６には
んだ付けするため、大きな実装面積が必要であるという
問題があった。また、ＢＧＡ等の高密度実装型半導体装
置は、少ない実装面積で実装が可能であるが、特殊な部
材を使用するため、従来の樹脂封止型半導体装置の生産
装置および生産技術が使えず、新たな技術開発および設
備投資が必要であり、製品化までの時間がかかり、コス
トが高いという問題があった。また、特開平１−１２８
８９２号公報で提案された半導体装置では、実装面積の
縮小は図られるが、ＩＣチップ２の電極とチップ搭載片
１１との位置合わせの必要から、ＩＣチップ２の電極の
位置等が制限され、設計上の自由度が低いという問題が
あった。As described above, in the conventional resin-encapsulated semiconductor device using the lead frame 3, the external leads 3 c derived from the encapsulating resin 1 are soldered to the circuit board 6. There is a problem that a large mounting area is required. In addition, high-density mounting type semiconductor devices such as BGA can be mounted in a small mounting area, but because of the use of special members, conventional resin-encapsulated semiconductor device production equipment and production technology cannot be used. There is a problem that new technology development and capital investment are required, time is required for commercialization, and cost is high. In addition, Japanese Patent Application Laid-Open No. 1-128
In the semiconductor device proposed in Japanese Patent No. 892, the mounting area can be reduced, but the position of the electrodes of the IC chip 2 is limited due to the necessity of aligning the electrodes of the IC chip 2 with the chip mounting pieces 11, There is a problem that the degree of freedom in design is low.
【０００５】本発明は、上記のような問題点を解消する
ためになされたもので、従来の樹脂封止型半導体装置の
生産装置および生産技術を使用でき、実装面積の縮小化
が可能な半導体装置とその製造方法を提供し、さらに
は、ＩＣ集積回路およびリードフレームの設計の自由度
が高い半導体装置を得ることを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and a semiconductor device capable of using a conventional resin-encapsulated semiconductor device production apparatus and production technology and having a reduced mounting area can be used. It is another object of the present invention to provide a device and a method of manufacturing the same, and to obtain a semiconductor device having a high degree of freedom in designing an IC integrated circuit and a lead frame.
【０００６】[0006]
【課題を解決するための手段】本発明に係わる半導体装
置は、リードフレームの上側表面に電極形成面を上向き
に搭載された半導体素子と、半導体素子をリードフレー
ムに固定する接着物質と、半導体素子の電極とリードフ
レームを電気的に接続するワイヤと、半導体素子、リー
ドフレームおよびワイヤ等を覆う封止樹脂と、リードフ
レームの下側表面の一部を封止樹脂底面より露出させて
なる端子部を備えたものである。また、リードフレーム
の上側表面に電極形成面を下向きに搭載された半導体素
子と、半導体素子の電極とリードフレームを電気的およ
び機械的に接続する導電性物質と、半導体素子およびリ
ードフレーム等を覆う封止樹脂と、リードフレームの下
側表面の一部を封止樹脂底面より露出させてなる端子部
を備え、リードフレーム端部のいずれかの片側表面を封
止樹脂の両側面より露出させたものである。さらに、封
止樹脂は、リードフレームを境にその上部が下部よりも
小さく形成され、リードフレーム端部の上側表面を封止
樹脂の両側面より露出させたものである。SUMMARY OF THE INVENTION A semiconductor device according to the present invention comprises a semiconductor element having an electrode-formed surface facing upward on an upper surface of a lead frame, an adhesive for fixing the semiconductor element to the lead frame, and a semiconductor element. A wire for electrically connecting the electrode to the lead frame, a sealing resin for covering the semiconductor element, the lead frame, the wires, and the like, and a terminal portion having a part of the lower surface of the lead frame exposed from the sealing resin bottom surface. It is provided with. A semiconductor element mounted on the upper surface of the lead frame with the electrode forming surface facing downward; a conductive material for electrically and mechanically connecting the electrode of the semiconductor element and the lead frame; and covering the semiconductor element and the lead frame. A sealing resin, and a terminal portion in which a part of the lower surface of the lead frame is exposed from the bottom surface of the sealing resin, and one surface of one end of the lead frame is exposed from both side surfaces of the sealing resin. Things. Further, the sealing resin is formed such that the upper part thereof is smaller than the lower part with the border of the lead frame, and the upper surface of the end portion of the lead frame is exposed from both side surfaces of the sealing resin.
【０００７】また、リードフレームの上側表面に電極形
成面を下向きに搭載された半導体素子と、半導体素子の
電極とリードフレームを電気的および機械的に接続する
導電性物質と、半導体素子およびリードフレーム等を覆
う封止樹脂と、リードフレームの下側表面の一部を封止
樹脂底面より露出させてなる端子部を備え、半導体素子
の上面すなわち電極が形成されていない面を封止樹脂よ
り露出させたものである。さらに、露出された半導体素
子上面に、放熱フィンを取り付けたものである。また、
リードフレームの上側表面に電極形成面を下向きに搭載
された半導体素子と、半導体素子の電極とリードフレー
ムを電気的および機械的に接続する導電性物質と、半導
体素子およびリードフレーム等を覆う封止樹脂と、リー
ドフレームの下側表面の一部を封止樹脂底面より露出さ
せてなる端子部を備え、リードフレームは、端子部を除
いてすべて封止樹脂内に封入されているものである。Also, a semiconductor element mounted on an upper surface of a lead frame with an electrode forming surface facing down, a conductive material for electrically and mechanically connecting an electrode of the semiconductor element and the lead frame, a semiconductor element and a lead frame And a terminal portion that exposes a part of the lower surface of the lead frame from the bottom surface of the sealing resin, and exposes the top surface of the semiconductor element, that is, the surface on which no electrodes are formed, from the sealing resin. It was made. Further, a radiation fin is attached to the exposed upper surface of the semiconductor element. Also,
A semiconductor element mounted on the upper surface of the lead frame with the electrode forming surface facing downward, a conductive substance for electrically and mechanically connecting the electrode of the semiconductor element and the lead frame, and a seal covering the semiconductor element and the lead frame, etc. A resin and a terminal portion having a part of the lower surface of the lead frame exposed from the bottom surface of the sealing resin are provided, and the lead frame except for the terminal portion is entirely sealed in the sealing resin.
【０００８】また、本発明に関わる半導体装置の製造方
法は、リードフレームの上側表面に半導体素子を搭載
し、これを封止樹脂で覆う工程と、リードフレームの底
面側よりレーザを照射し封止樹脂を除去して、リードフ
レームの下側表面の一部を封止樹脂底面より露出させ、
端子部を形成する工程を含んで製造するようにしたもの
である。In a method of manufacturing a semiconductor device according to the present invention, a semiconductor element is mounted on an upper surface of a lead frame and the semiconductor element is covered with a sealing resin. Removing the resin, exposing a part of the lower surface of the lead frame from the sealing resin bottom surface,
The manufacturing method includes a step of forming a terminal portion.
【０００９】[0009]
実施の形態１．以下、本発明の実施の形態１である半導
体装置を図について説明する。図１は、本発明の実施の
形態１である樹脂封止型半導体装置の構造を示す断面図
である。図において、１は封止樹脂、２は半導体素子で
あるＩＣ集積回路、３はリードフレーム、３ａは端子
部、４はＩＣ集積回路２の電極とリードフレーム３を電
気的に接続するワイヤで、例えば金線、５はＩＣ集積回
路２をリードフレーム３に固定するための接着物質、６
は半導体装置を実装する回路基板、７は回路基板６の電
極部、８はリードフレーム３の端子部３ａと回路基板６
の電極部７とを接続する導電性物質で、例えばはんだペ
ーストである。本実施の形態では、リードフレーム３の
上側表面に、電極（図示せず）形成面を上向きにＩＣ集
積回路２を搭載し、ＩＣ集積回路２の電極とリードフレ
ーム３をワイヤ４で電気的に接続したものを封止樹脂１
で覆い、リードフレーム３の下側表面の一部を封止樹脂
１底面より露出させて外部接続用の端子部３ａとしたも
のである。リードフレーム３は、その下側表面の一部を
封止樹脂１底面より露出させるために、折り曲げられて
いる。Embodiment 1 FIG. Hereinafter, a semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing the structure of the resin-sealed semiconductor device according to the first embodiment of the present invention. In the figure, 1 is a sealing resin, 2 is an IC integrated circuit as a semiconductor element, 3 is a lead frame, 3a is a terminal portion, 4 is a wire for electrically connecting an electrode of the IC integrated circuit 2 and the lead frame 3, For example, the gold wire 5 is an adhesive material for fixing the IC integrated circuit 2 to the lead frame 3, 6
Is a circuit board on which the semiconductor device is mounted, 7 is an electrode portion of the circuit board 6, and 8 is a terminal portion 3a of the lead frame 3 and the circuit board 6.
And a conductive material for connecting the electrode portion 7 with the electrode portion 7, for example, a solder paste. In this embodiment, the IC integrated circuit 2 is mounted on the upper surface of the lead frame 3 with the electrode (not shown) forming surface facing upward, and the electrodes of the IC integrated circuit 2 and the lead frame 3 are electrically connected by wires 4. Connect the sealing resin 1
And a part of the lower surface of the lead frame 3 is exposed from the bottom surface of the sealing resin 1 to form a terminal portion 3a for external connection. The lead frame 3 is bent to expose a part of the lower surface from the bottom surface of the sealing resin 1.
【００１０】本実施の形態による半導体装置は、リード
フレーム３の下側表面を封止樹脂１の底面から露出させ
外部接続用の端子部３ａとする半導体装置であって、Ｉ
Ｃ集積回路２の電極とリードフレーム３をワイヤ４で電
気的に接続することを特徴とする。リードフレーム３と
ＩＣ集積回路２は接着物質５を介して固定されるため、
ＩＣ集積回路２の高さが一定に保持され、ワイヤ４を接
続するときに安定したボンディング結果が得られる。本
実施の形態による半導体装置は、前述の図８に示すリー
ドフレーム３とＩＣ集積回路２の電極を半田バンプ１３
で接合する従来の半導体装置と比較して、ＩＣ集積回路
２およびリードフレーム３の設計の自由度が大きい。す
なわち、前述の従来装置では、リードフレーム３とＩＣ
集積回路２の電極の位置合わせの必要があるのに対し
て、本実施の形態による半導体装置では、ワイヤ４で接
合を行うため、ＩＣ集積回路２の電極の位置は特に制限
されず、１つのリードフレーム３で、数種類のＩＣ集積
回路に対応することも可能である。The semiconductor device according to the present embodiment is a semiconductor device in which a lower surface of a lead frame 3 is exposed from a bottom surface of a sealing resin 1 to be a terminal portion 3a for external connection.
The electrode of the C integrated circuit 2 and the lead frame 3 are electrically connected by wires 4. Since the lead frame 3 and the IC integrated circuit 2 are fixed via the adhesive material 5,
The height of the IC integrated circuit 2 is kept constant, and a stable bonding result is obtained when the wires 4 are connected. In the semiconductor device according to the present embodiment, the electrodes of the lead frame 3 and the IC integrated circuit 2 shown in FIG.
The degree of freedom in designing the IC integrated circuit 2 and the lead frame 3 is greater than that of a conventional semiconductor device joined by a conventional method. That is, in the conventional device described above, the lead frame 3 and the IC
While it is necessary to align the electrodes of the integrated circuit 2, the semiconductor device according to the present embodiment performs bonding with the wires 4, so that the positions of the electrodes of the IC integrated circuit 2 are not particularly limited. The lead frame 3 can support several types of IC integrated circuits.
【００１１】以上のように構成された半導体装置は、従
来の一般的な樹脂封止型半導体装置を回路基板６に実装
する場合に必要であったリードフレームの外部リードが
不要となるため、実装面積の縮小が図られる。また、ダ
イパット（図示せず）を使用した従来構造より半導体装
置の厚さが薄くでき、小型化が図られる。さらに、外部
リードに変わって、封止樹脂１底面よりリードフレーム
３を露出して端子部３ａとし、回路基板６と接続するこ
とにより、この端子部３ａの平坦性は、従来の外部リー
ド３ｃの平坦性に比べ格段に良く、リード変形もないた
め安定した実装性が得られる。また、実装時のはんだペ
ースト等の導電性物質８の塗布量を低減することがで
き、よりファインピッチの半導体装置を得ることができ
る。また、本実施の形態による半導体装置は、リードフ
レーム３を使用するため、従来の生産装置および生産技
術を広範囲で用いることができ、且つリード加工工程に
おける曲げ工程が不要となり、容易かつ安価に高密度半
導体装置を生産することが可能である。さらに、外部リ
ード３ｃがないため、製品の取り扱いが容易であり、梱
包資材の簡易化も可能であるため、輸送コストも低減で
きる。The semiconductor device constructed as described above does not require external leads of a lead frame, which is necessary when a conventional general resin-encapsulated semiconductor device is mounted on the circuit board 6. The area can be reduced. Further, the thickness of the semiconductor device can be made smaller than that of the conventional structure using a die pad (not shown), and the size can be reduced. Further, in place of the external lead, the lead frame 3 is exposed from the bottom surface of the sealing resin 1 to form a terminal portion 3a and is connected to the circuit board 6, so that the flatness of the terminal portion 3a is reduced to the level of the conventional external lead 3c. It is much better than flatness, and stable mounting is obtained because there is no lead deformation. Further, the amount of the conductive substance 8 such as a solder paste applied at the time of mounting can be reduced, and a semiconductor device with a finer pitch can be obtained. In addition, since the semiconductor device according to the present embodiment uses the lead frame 3, the conventional production apparatus and production technology can be used in a wide range, and the bending step in the lead processing step is not required. It is possible to produce high density semiconductor devices. Further, since there is no external lead 3c, the handling of the product is easy and the packaging material can be simplified, so that the transportation cost can be reduced.
【００１２】実施の形態２．図２は、本発明の実施の形
態２である樹脂封止型半導体装置の構造を示す断面図で
ある。図において、３ｂはリードフレーム３の露出部、
９はＩＣ集積回路２の電極とリードフレーム３を接続す
る導電性物質である。なお図中、同一、相当部分には同
一符号を付し、説明を省略する。本実施の形態による半
導体装置は、リードフレーム３の上側表面に電極（図示
せず）形成面を下向きにＩＣ集積回路２を搭載し、この
ＩＣ集積回路２の電極とリードフレーム３を導電性物質
９で電気的および機械的に接続し、ＩＣ集積回路２およ
びリードフレーム３等を封止樹脂１で覆い、リードフレ
ーム３の下側表面の一部を封止樹脂１底面より露出させ
て端子部３ａとする半導体装置であって、リードフレー
ム３端部のいずれかの片側表面、本実施の形態では上側
表面を封止樹脂１の両側面より露出させたことを特徴と
する。具体的には、リードフレーム３を境にして封止樹
脂１の上部を下部よりも小さく形成し、リードフレーム
３端部の上側表面を封止樹脂１の両側面より露出させた
ものである。Embodiment 2 FIG. FIG. 2 is a sectional view showing the structure of the resin-encapsulated semiconductor device according to the second embodiment of the present invention. In the figure, 3b is an exposed portion of the lead frame 3,
Reference numeral 9 denotes a conductive substance that connects the electrodes of the IC integrated circuit 2 and the lead frame 3. In the drawings, the same or corresponding portions are denoted by the same reference characters, and description thereof is omitted. In the semiconductor device according to the present embodiment, the IC integrated circuit 2 is mounted on the upper surface of the lead frame 3 with the electrode (not shown) formed face down, and the electrodes of the IC integrated circuit 2 and the lead frame 3 are made of a conductive material. 9, the IC integrated circuit 2 and the lead frame 3 are covered with the sealing resin 1, and a part of the lower surface of the lead frame 3 is exposed from the bottom surface of the sealing resin 1 to form a terminal portion. A semiconductor device designated by reference numeral 3a, characterized in that one surface of one end of the lead frame 3, in this embodiment, the upper surface is exposed from both side surfaces of the sealing resin 1. Specifically, the upper part of the sealing resin 1 is formed smaller than the lower part with the lead frame 3 as a boundary, and the upper surface of the end of the lead frame 3 is exposed from both side surfaces of the sealing resin 1.
【００１３】以上のように構成された半導体装置は、リ
ードフレーム３の露出部３ｂを介して実装試験を電気的
に行うことができる。本実施の形態による半導体装置
は、実装部分が半導体装置の裏面部分にあり目視検査が
困難であるため、それに代わる試験方法として、例えば
導電テスタの検査端子をリードフレーム３の露出部３ｂ
に接触させることにより実装試験を行うことができる。
図８に示す従来の半導体装置では、リードフレーム３の
端部が封止樹脂１の両側面より突出した構造をとってい
るが、本実施の形態における半導体装置では、リードフ
レーム３端部の片側表面のみを封止樹脂１より露出させ
ているため、導電テスタの検査端子を押し当てる時に変
形などの心配がなく、安定した接触が行える点で優れて
いる。さらに、リードフレーム３が突き出ていないた
め、露出部３ｂの変形が無く形状が安定しており、製品
の取り扱いが容易となる。The semiconductor device configured as described above can electrically perform a mounting test via the exposed portion 3b of the lead frame 3. Since the semiconductor device according to the present embodiment has a mounting portion on the back surface portion of the semiconductor device and is difficult to visually inspect, as an alternative test method, for example, the test terminal of the conductive tester is connected to the exposed portion 3b of the lead frame 3.
A mounting test can be performed by contacting the device.
Although the conventional semiconductor device shown in FIG. 8 has a structure in which the ends of the lead frame 3 protrude from both side surfaces of the sealing resin 1, the semiconductor device according to the present embodiment has one end of the lead frame 3 on one side. Since only the surface is exposed from the sealing resin 1, there is no need to worry about deformation or the like when pressing the inspection terminal of the conductive tester, which is excellent in that stable contact can be performed. Further, since the lead frame 3 does not protrude, the exposed portion 3b is not deformed and has a stable shape, and the product can be easily handled.
【００１４】実施の形態３．図３は、本発明の実施の形
態３である樹脂封止型半導体装置の構造を示す断面図で
ある。なお図中、同一、相当部分には同一符号を付し、
説明を省略する。本実施の形態による半導体装置は、リ
ードフレーム３の上側表面に電極（図示せず）形成面を
下向きにＩＣ集積回路２を搭載し、このＩＣ集積回路２
の電極とリードフレーム３を導電性物質９で電気的およ
び機械的に接続し、ＩＣ集積回路２およびリードフレー
ム３等を封止樹脂１で覆い、リードフレーム３の下側表
面の一部を封止樹脂１底面より露出させて端子部３ａと
する半導体装置であって、ＩＣ集積回路２の上面すなわ
ち電極が形成されていない面を封止樹脂１より露出させ
たことを特徴とする。具体的には、封止樹脂１の上部を
省略して形成したものである。Embodiment 3 FIG. 3 is a sectional view showing the structure of the resin-encapsulated semiconductor device according to the third embodiment of the present invention. In the drawings, the same or corresponding parts are denoted by the same reference numerals,
Description is omitted. In the semiconductor device according to the present embodiment, an IC integrated circuit 2 is mounted on an upper surface of a lead frame 3 with an electrode (not shown) formed surface facing downward.
And the lead frame 3 are electrically and mechanically connected with a conductive substance 9, the IC integrated circuit 2 and the lead frame 3 are covered with the sealing resin 1, and a part of the lower surface of the lead frame 3 is sealed. A semiconductor device that is exposed from the bottom surface of the sealing resin 1 to be a terminal portion 3a, wherein an upper surface of the IC integrated circuit 2, that is, a surface on which no electrode is formed is exposed from the sealing resin 1. Specifically, it is formed by omitting the upper part of the sealing resin 1.
【００１５】以上のように構成された半導体装置は、Ｉ
Ｃ集積回路２より発生する熱を効率よく放熱でき、さら
に、実装時の急激な温度上昇に対する封止樹脂１および
各構成部品の界面付近に存在する水分の急激な膨張によ
る半導体装置の破壊を防止することができる。また、半
導体装置の封止樹脂１が占める体積比率が減少するた
め、封止樹脂１、ＩＣ集積回路２およびリードフレーム
３の熱膨張係数の違いによる半導体装置の歪みや反りが
低減でき、上記実施の形態１および２よりも高い平坦性
を得ることができ、良好な実装結果を得ることができ
る。さらに、本実施の形態による半導体装置の製造に用
いられる樹脂封止金型の片側、本例では上型は、平坦な
板でよいので、金型の構成が簡略化でき低コスト化が可
能である。The semiconductor device configured as described above has
The heat generated from the C integrated circuit 2 can be efficiently dissipated, and furthermore, the semiconductor device is prevented from being destroyed due to a rapid expansion of moisture existing near the interface between the sealing resin 1 and each component due to a rapid temperature rise during mounting. can do. Further, since the volume ratio occupied by the sealing resin 1 of the semiconductor device is reduced, distortion and warpage of the semiconductor device due to differences in the thermal expansion coefficients of the sealing resin 1, the IC integrated circuit 2 and the lead frame 3 can be reduced. It is possible to obtain higher flatness than in the first and second embodiments, and to obtain a good mounting result. Further, since one side of the resin-sealing mold used for manufacturing the semiconductor device according to the present embodiment, in this example, the upper mold may be a flat plate, the structure of the mold can be simplified and the cost can be reduced. is there.
【００１６】実施の形態４．図４は、本発明の実施の形
態４である樹脂封止型半導体装置の構造を示す断面図で
ある。図において、１０は封止樹脂１から露出されたＩ
Ｃ集積回路２上面に取り付けられた放熱フィンである。
なお図中、同一、相当部分には同一符号を付し、説明を
省略する。本実施の形態では、前述の実施の形態３によ
る半導体装置においてＩＣ集積回路２の上面に放熱フィ
ン１０を接続することにより、ＩＣ集積回路２より発生
する熱をさらに効率よく放熱するものであり、半導体装
置の急激な温度上昇による破壊をより効果的に防止する
ことが可能である。Embodiment 4 FIG. 4 is a sectional view showing a structure of a resin-encapsulated semiconductor device according to a fourth embodiment of the present invention. In the drawing, reference numeral 10 denotes I exposed from the sealing resin 1.
Radiation fins mounted on the upper surface of the C integrated circuit 2.
In the drawings, the same or corresponding portions are denoted by the same reference characters, and description thereof is omitted. In the present embodiment, the heat generated by the IC integrated circuit 2 is more efficiently radiated by connecting the radiation fin 10 to the upper surface of the IC integrated circuit 2 in the semiconductor device according to the third embodiment. It is possible to more effectively prevent the semiconductor device from being broken due to a rapid temperature rise.
【００１７】実施の形態５．図５は、本発明の実施の形
態５である樹脂封止型半導体装置の構造を示す断面図で
ある。本実施の形態による半導体装置は、リードフレー
ム３の上側表面に電極（図示せず）形成面を下向きにＩ
Ｃ集積回路２を搭載し、このＩＣ集積回路２の電極とリ
ードフレーム３を導電性物質９で電気的および機械的に
接続し、ＩＣ集積回路２およびリードフレーム３等を封
止樹脂１で覆い、リードフレーム３の下側表面の一部を
封止樹脂１底面より露出させて端子部３ａとする半導体
装置であって、リードフレーム３は、端子部３ａを除い
てすべて封止樹脂１内に封入されていることを特徴とす
る。以上のように構成された半導体装置は、リードフレ
ーム３両側面からの突き出し部がないため、製品の取り
扱いが容易であり、梱包資材の簡易化も可能となり、輸
送コストも低減できる。Embodiment 5 FIG. 5 is a sectional view showing the structure of the resin-encapsulated semiconductor device according to the fifth embodiment of the present invention. In the semiconductor device according to the present embodiment, the upper surface of the lead frame 3 has an electrode (not shown) formed face down.
The C integrated circuit 2 is mounted, and the electrodes of the IC integrated circuit 2 and the lead frame 3 are electrically and mechanically connected by a conductive substance 9, and the IC integrated circuit 2, the lead frame 3 and the like are covered with the sealing resin 1. A semiconductor device in which a part of the lower surface of the lead frame 3 is exposed from the bottom surface of the sealing resin 1 to be a terminal portion 3a, and the lead frame 3 is entirely in the sealing resin 1 except for the terminal portion 3a. It is characterized by being enclosed. Since the semiconductor device configured as described above has no protruding portions from both side surfaces of the lead frame 3, it is easy to handle the product, the packaging material can be simplified, and the transportation cost can be reduced.
【００１８】本実施の形態による半導体装置の製造方法
を図６に示す。リードフレーム３の上側表面に電極形成
面を下向きにしてＩＣ集積回路２を搭載し、導電性物質
９で接続したものを封止樹脂１で覆った後、リードフレ
ーム３の底面側よりレーザを照射し（図６（ａ））、封
止樹脂１を除去してリードフレーム３の下側表面の一部
を露出させ、端子部３ａを形成する（図６（ｂ））。リ
ードフレーム３の露出面を、封止樹脂１面よりも０. ０
１mmから０. ２mm程度高く加工することにより、回路基
板６に実装するときにフィレットが形成でき、良好な実
装結果が得られる。FIG. 6 shows a method of manufacturing the semiconductor device according to the present embodiment. The IC integrated circuit 2 is mounted on the upper surface of the lead frame 3 with the electrode forming surface facing downward, and the one connected with the conductive substance 9 is covered with the sealing resin 1 and then the laser is irradiated from the bottom side of the lead frame 3. Then, the sealing resin 1 is removed to expose a part of the lower surface of the lead frame 3 to form a terminal portion 3a (FIG. 6B). The exposed surface of the lead frame 3 is set at 0.0 more than the sealing resin 1 surface.
By processing from 1 mm to about 0.2 mm higher, a fillet can be formed when mounted on the circuit board 6, and good mounting results can be obtained.
【００１９】[0019]
【発明の効果】以上のように、本発明における半導体装
置によれば、リードフレームの上側表面に電極形成面を
上向きに半導体素子を搭載し、リードフレームの下側表
面の一部を封止樹脂底面より露出させ外部接続用の端子
部とし、半導体素子の電極とリードフレームをワイヤで
接続するようにしたので、半導体素子およびリードフレ
ームの設計の自由度が大きく、また、リードフレームの
外部リードが不要となるため装置の小型化が図られ、実
装面積の縮小化が可能となる。As described above, according to the semiconductor device of the present invention, the semiconductor element is mounted on the upper surface of the lead frame with the electrode forming surface facing upward, and a part of the lower surface of the lead frame is sealed with the sealing resin. Exposed from the bottom surface and used as a terminal for external connection, the electrodes of the semiconductor element and the lead frame are connected by wires, so the degree of freedom in designing the semiconductor element and the lead frame is large, and the external leads of the lead frame are Since it becomes unnecessary, the size of the device can be reduced, and the mounting area can be reduced.
【００２０】また、リードフレームを使用するため、従
来の生産装置および生産技術を広範囲で用いることがで
き、容易かつ安価に半導体装置を生産することが可能で
ある。Further, since a lead frame is used, conventional production equipment and production technology can be used in a wide range, and semiconductor devices can be produced easily and at low cost.
【図１】 この発明の実施の形態１である半導体装置の
構造を示す断面図である。FIG. 1 is a sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention;
【図２】 この発明の実施の形態２である半導体装置の
構造を示す断面図である。FIG. 2 is a sectional view showing a structure of a semiconductor device according to a second embodiment of the present invention;
【図３】 この発明の実施の形態３である半導体装置の
構造を示す断面図である。FIG. 3 is a sectional view showing a structure of a semiconductor device according to a third embodiment of the present invention;
【図４】 この発明の実施の形態４である半導体装置の
構造を示す断面図である。FIG. 4 is a sectional view showing a structure of a semiconductor device according to a fourth embodiment of the present invention;
【図５】 この発明の実施の形態５である半導体装置の
構造を示す断面図である。FIG. 5 is a sectional view showing a structure of a semiconductor device according to a fifth embodiment of the present invention;
【図６】 この発明の実施の形態５である半導体装置の
製造方法を示す断面図である。FIG. 6 is a sectional view illustrating a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention;
【図７】 従来の半導体装置の構造を示す断面図であ
る。FIG. 7 is a cross-sectional view illustrating a structure of a conventional semiconductor device.
【図８】 従来の半導体装置の構造を示す断面図であ
る。FIG. 8 is a cross-sectional view illustrating a structure of a conventional semiconductor device.
１ 封止樹脂、２ ＩＣ集積回路、３ リードフレー
ム、３ａ 端子部、３ｂ 露出部、３ｃ 外部リード、
４ ワイヤ、５ 接着物質、６ 回路基板、７ 電極
部、８、９ 導電性物質、１０ 放熱フィン、１１ チ
ップ搭載片、１２ 端子、１３ 半田バンプ。1 sealing resin, 2 IC integrated circuit, 3 lead frame, 3a terminal portion, 3b exposed portion, 3c external lead,
4 wire, 5 adhesive substance, 6 circuit board, 7 electrode part, 8, 9 conductive substance, 10 heat radiation fin, 11 chip mounting piece, 12 terminal, 13 solder bump.
Claims (7)
を上向きに搭載された半導体素子、 上記半導体素子を上記リードフレームに固定する接着物
質、 上記半導体素子の電極と上記リードフレームを電気的に
接続するワイヤ、 上記半導体素子、上記リードフレームおよび上記ワイヤ
等を覆う封止樹脂、 上記リードフレームの下側表面の一部を上記封止樹脂底
面より露出させてなる端子部を備えたことを特徴とする
半導体装置。1. A semiconductor element having an electrode formation surface facing upward on an upper surface of a lead frame, an adhesive material for fixing the semiconductor element to the lead frame, and electrically connecting an electrode of the semiconductor element to the lead frame. A sealing resin covering the semiconductor element, the lead frame, the wires, and the like, and a terminal portion exposing a part of a lower surface of the lead frame from the bottom surface of the sealing resin. Semiconductor device.
を下向きに搭載された半導体素子、 上記半導体素子の電極と上記リードフレームを電気的お
よび機械的に接続する導電性物質、 上記半導体素子および上記リードフレーム等を覆う封止
樹脂、 上記リードフレームの下側表面の一部を上記封止樹脂底
面より露出させてなる端子部を備え、上記リードフレー
ム端部のいずれかの片側表面を上記封止樹脂の両側面よ
り露出させたことを特徴とする半導体装置。2. A semiconductor element mounted on an upper surface of a lead frame with an electrode forming surface facing down, a conductive substance electrically and mechanically connecting an electrode of the semiconductor element and the lead frame, the semiconductor element and the semiconductor element. A sealing resin for covering the lead frame, etc .; a terminal portion having a part of the lower surface of the lead frame exposed from the bottom surface of the sealing resin; A semiconductor device exposed from both sides of a resin.
上部が下部よりも小さく形成され、上記リードフレーム
端部の上側表面を上記封止樹脂の両側面より露出させた
ことを特徴とする請求項２記載の半導体装置。3. The sealing resin is formed such that an upper part thereof is smaller than a lower part thereof with a lead frame as a boundary, and an upper surface of an end of the lead frame is exposed from both side surfaces of the sealing resin. The semiconductor device according to claim 2.
を下向きに搭載された半導体素子、 上記半導体素子の電極と上記リードフレームを電気的お
よび機械的に接続する導電性物質、 上記半導体素子および上記リードフレーム等を覆う封止
樹脂、 上記リードフレームの下側表面の一部を上記封止樹脂底
面より露出させてなる端子部を備え、上記半導体素子の
上面すなわち電極が形成されていない面を上記封止樹脂
より露出させたことを特徴とする半導体装置。4. A semiconductor element mounted on an upper surface of a lead frame with an electrode forming surface facing downward, a conductive substance for electrically and mechanically connecting an electrode of the semiconductor element and the lead frame, the semiconductor element and the semiconductor element. A sealing resin for covering the lead frame and the like; a terminal portion formed by exposing a part of the lower surface of the lead frame from the bottom surface of the sealing resin; A semiconductor device exposed from a sealing resin.
ンを取り付けたことを特徴とする請求項４記載の半導体
装置。5. The semiconductor device according to claim 4, wherein a radiation fin is attached to the exposed upper surface of the semiconductor element.
を下向きに搭載された半導体素子、 上記半導体素子の電極と上記リードフレームを電気的お
よび機械的に接続する導電性物質、 上記半導体素子および上記リードフレーム等を覆う封止
樹脂、 上記リードフレームの下側表面の一部を上記封止樹脂底
面より露出させてなる端子部を備え、上記リードフレー
ムは、上記端子部を除いてすべて上記封止樹脂内に封入
されていることを特徴とする半導体装置。6. A semiconductor element mounted on an upper surface of a lead frame with an electrode forming surface facing downward, a conductive material for electrically and mechanically connecting an electrode of the semiconductor element and the lead frame, the semiconductor element and the semiconductor element. A sealing resin for covering the lead frame, etc., a terminal portion having a part of the lower surface of the lead frame exposed from the sealing resin bottom surface, and the lead frame is entirely sealed except for the terminal portion. A semiconductor device which is sealed in a resin.
を搭載し、これを封止樹脂で覆う工程、上記リードフレ
ームの底面側よりレーザを照射し上記封止樹脂を除去し
て、上記リードフレームの下側表面の一部を上記封止樹
脂底面より露出させ、端子部を形成する工程を含むこと
を特徴とする半導体装置の製造方法。7. A step of mounting a semiconductor element on an upper surface of a lead frame and covering the same with a sealing resin, irradiating a laser from a bottom side of the lead frame to remove the sealing resin, and removing the sealing resin. A method of manufacturing a semiconductor device, comprising a step of exposing a part of a lower surface from the bottom surface of the sealing resin to form a terminal portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22476397A JPH1168005A (en) | 1997-08-21 | 1997-08-21 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22476397A JPH1168005A (en) | 1997-08-21 | 1997-08-21 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1168005A true JPH1168005A (en) | 1999-03-09 |
Family
ID=16818855
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22476397A Pending JPH1168005A (en) | 1997-08-21 | 1997-08-21 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1168005A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008088291A1 (en) * | 2007-01-16 | 2008-07-24 | Infineon Technologies Ag | Method of semiconductor packaging and/or a semiconductor package |
| JP2019161086A (en) * | 2018-03-15 | 2019-09-19 | エイブリック株式会社 | Semiconductor device and manufacturing method thereof |
-
1997
- 1997-08-21 JP JP22476397A patent/JPH1168005A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008088291A1 (en) * | 2007-01-16 | 2008-07-24 | Infineon Technologies Ag | Method of semiconductor packaging and/or a semiconductor package |
| US7939381B2 (en) | 2007-01-16 | 2011-05-10 | Infineon Technologies Ag | Method of semiconductor packaging and/or a semiconductor package |
| JP2019161086A (en) * | 2018-03-15 | 2019-09-19 | エイブリック株式会社 | Semiconductor device and manufacturing method thereof |
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