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JP4038021B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP4038021B2
JP4038021B2 JP2000546392A JP2000546392A JP4038021B2 JP 4038021 B2 JP4038021 B2 JP 4038021B2 JP 2000546392 A JP2000546392 A JP 2000546392A JP 2000546392 A JP2000546392 A JP 2000546392A JP 4038021 B2 JP4038021 B2 JP 4038021B2
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semiconductor chip
bga
tape
reinforcing frame
semiconductor device
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典之 高橋
誠一 市原
忠一 宮崎
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Renesas Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

技術分野
本発明は、半導体装置およびその製造方法に関し、特に、半導体チップを搭載したパッケージ基板を半田バンプを介してフリント配線基板に実装するボールグリッドアレイ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ；ＢＧＡ）型の半導体装置に適用して有効な技術に関する。
背景技術
半導体チップを搭載したパッケージ基板の一面に半田バンプを取り付け、この半田バンプを介してパッケージ基板をプリント配線基板に実装するＢＧＡは、パッケージの側面からリードを引き出したＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）やＳＯＰ（Ｓｍａｌｌ Ｏｕｔｌｉｎｅ Ｐａｃｋａｇｅ）などに比べて多ピン化が容易で、かつ実装面積も小さくできるという利点がある。
上記ＢＧＡには各種の構造が提案されているが、特に携帯情報機器、ディジタルカメラ、ノートパソコンといった小型軽量電子機器への実装に好適なＢＧＡとして、パッケージ基板を絶縁テープで構成したＴＣＰ（Ｔａｐｅ Ｃａｒｒｉｅｒ Ｐａｃｋａｇｅ）方式のＢＧＡ（テープＢＧＡ）が公知である。この種のテープＢＧＡについては、例えば特開平７−３２１２４８号公報、特開平８−８８２４３号公報、特開平８−１１１４３３号公報などに記載がある。
また、本発明者は、以下のような構造のＢＧＡ（特に、バンプのピッチを狭小化したファインピッチＢＧＡ）を開発している。このＢＧＡは、片面にＣｕ（銅）箔からなる複数のリードを形成した樹脂製の配線基板の中央部にデバイスホールを形成してそこに半導体チップを配置し、この半導体チップとリードの一端部とをＡｕのバンプ電極を介して電気的に接続すると共に、半導体チップの主面をポッティング樹脂で封止する。また、リードの他端部を配線基板の周辺部まで延在してランド部を形成し、そこにＢＧＡの外部接続端子となる半田バンプを接続する。
さらに、上記ＢＧＡを組立てる工程で半田バンプをランド部に確実に位置決めできるようにするための補強材として、配線基板の周辺部の半田バンプ接合面と反対側の面に四角枠状の金属枠を接着剤で貼り付け、この金属枠で配線基板の周辺部の反りを防いでいる。
しかし、上記のＢＧＡで使用する金属枠は、Ｃｕ（銅）などの薄い金属板をプレスで打ち抜いて片面に接着剤を塗布し、さらにその表面に接着剤保護用のカバーテープを貼り付けたものであるために材料が高価であり、ＢＧＡの製造コストを引き上げる要因となる。また、配線基板に金属枠を貼り付ける作業が必要となるために、ＢＧＡの製造工程が増える。この金属枠を貼り付ける作業は、接着剤を保護する薄いカバーテープを剥がす作業がロボットハンドでは上手く処理出来ないために、自動化によってコスト削減を図ることも難しい。
本発明の目的は、ＢＧＡ（テープＢＧＡ、ファインピッチＢＧＡなど）の製造コストを低減することのできる技術を提供することにある。
本発明の他の目的は、ＢＧＡ（テープＢＧＡ、ファインピッチＢＧＡなど）の信頼性を向上することのできる技術を提供することにある。
本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。
発明の開示
本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、以下の通りである。
本発明の半導体装置は、半導体チップと、前記半導体チップを囲むように設けられた配線基板と、前記配線基板に形成され、一端部が前記半導体チップと電気的に接続された複数のリードと、前記半導体チップを被覆する封止樹脂と、前記配線基板の一面の周辺部に沿って配置され、前記リードの他端部と電気的に接続された複数個のバンプと、前記配線基板の他面の周辺部に沿って設けられ、前記配線基板を挟んで前記複数個のバンプと対向するように配置された樹脂製の補強枠とを有する。
また、本発明の半導体装置は、半導体チップと、前記半導体チップを囲むように設けられた配線基板と、前記配線基板に形成され、一端部が前記半導体チップと電気的に接続された複数のリードと、前記半導体チップを被覆する封止樹脂と、前記配線基板の一面の周辺部に沿って設けられた補強枠と、前記補強枠に形成された複数個の凹溝の内部に配置され、前記リードの他端部と電気的に接続された複数個のバンプとを有する。
また、本発明の半導体装置は、半導体チップと、前記半導体チップを囲むように設けられた配線基板と、前記配線基板に形成され、一端部が前記半導体チップと電気的に接続された複数のリードと、前記半導体チップを被覆する封止樹脂と、前記配線基板の一面の周辺部に沿って配置され、前記リードの他端部と電気的に接続された複数個のバンプと、前記配線基板の他面の周辺部に沿って設けられ、前記配線基板を挟んで前記複数個のバンプと対向するように配置された樹脂製の補強枠とを有し、前記半導体チップは、その裏面が前記封止樹脂から露出している。
また、本発明の半導体装置の製造方法は、以下の工程を含んでいる。
（ａ）一端部がデバイスホールの内側に延在し、他の一部にバンプを接続するためのランド部が形成された複数のリードを有するテープ基材の前記デバイスホールに半導体チップを配置し、前記半導体チップと前記リードの一端部とを電気的に接続する工程、
（ｂ）前記半導体チップを被覆する封止樹脂と、前記配線基板の一面の周辺部に沿って設けられる補強枠とをトランスファ・モールド法によって成形する工程、
（ｃ）前記複数のリードのランド部にバンプを接続し、前記配線基板を挟んで前記バンプと前記補強枠とを対向するように配置する工程、
（ｄ）前記テープ基材の不要箇所を除去する工程。
上記した本発明によれば、配線基板に高価な金属枠を設ける工程が不要となるので、材料原価および製造工程数を低減することができ、低コストのＢＧＡを提供することができる。また、半導体チップをトランスファ・モールド法で樹脂封止することにより、信頼性の向上したＢＧＡを提供することができる。
発明を実施するための最良の形態
以下、本発明の実施形態を図面に基づいて詳細に説明する。なお、実施形態を説明するための全図において同一機能を有するものは同一の符号を付し、その繰り返しの説明は省略する。
実施形態１
図１は、本実施形態のテープＢＧＡ（ファインピッチＢＧＡ）を示す斜視図、図２は、このテープＢＧＡの実装面（半田バンプ取り付け面）を示す斜視図、図３は、このテープＢＧＡの断面図である。
本実施形態のテープＢＧＡは、片面に銅箔配線からなる複数のリード１を形成したポリイミド系樹脂からなる配線基板２、この配線基板２のデバイスホールに配置された半導体チップ３、この半導体チップ３を被覆する封止樹脂４、配線基板２０周辺部に沿って設けられた四角枠状の補強枠５、および配線基板２の周辺部に沿って取り付けられた複数個の半田バンプ６により構成されている。
マイコン、ＡＳＩＣなどのＬＳＩが形成された半導体チップ３は、その主面の周辺部に設けられたＡｕのバンプ電極７を介してリード１の一端部（インナーリード部１Ａ）と電気的に接続されている。リード１の他端部は、配線基板２の周辺部に設けられた補強枠５の下部まで延在し、この領域で半田バンプ６と電気的に接続されている。半田バンプ６が接合されたリード１の他端部（ランド部１Ｂ）を除く配線基板２の片面は、リード１を保護するためのソルダーレジスト（図示せず）で被覆されている。
配線基板２の周辺部、すなわち半田バンプ６が取り付けられた領域に設けられた補強枠５は、配線基板２０周辺部の平坦性を確保し、後述する半田バンプ６の取り付け工程で半田バンプ６がランド部１Ｂに確実に接合されるように機能する。この補強枠５は、トランスファ・モールド法によって成形された合成樹脂で構成されている。
半導体チップ３を外部環境から保護する封止樹脂４は、上記補強枠５と同じくトランスファ・モールド法によって成形された合成樹脂で構成され、半導体チップ３の全面を覆っている。図１に示すように、封止樹脂４は、その四隅において補強枠５と連結され、この補強枠５と一体に成形されている。
上記したテープＢＧＡの各部の材料、寸法の一例を示すと、半導体チップ３は単結晶シリコンからなり、その寸法は７．６ｍｍ×７．６ｍｍ、厚さ０．４ｍｍである。ポリイミド系樹脂からなる配線基板２の寸法は１５ｍｍ×１５ｍｍ、厚さ０．０７５ｍｍである。リード１は、この配線基板２の片面に貼り付けた厚さ０．０１８ｍｍの電解銅箔（または圧延銅箔）をエッチングして形成した銅箔配線からなり、その両端部（インナーリード部１Ａおよびランド部１Ｂ）の表面には、Ａｕ／Ｎｉのメッキが施されている。
半導体チップ３を封止する封止樹脂４およびこれと一体に成形された補強枠５は、シリカなどのフィラーが充填されたエポキシ系樹脂からなる。封止樹脂４の寸法は１４．６ｍｍ×１４．６ｍｍ、厚さ０．６５５ｍｍである。補強枠５は、配線基板２の片面のみに形成され、その厚さは０．３５５ｍｍである。リード１のランド部１Ｂに接合された半田バンプ７はＳｎ（６３％）／Ｐｂ（３７％）合金からなり、その直径は０．３ｍｍ、ピッチは０．５ｍｍである。
次に、上記のように構成された本実施形態のテープＢＧＡの製造方法を図４〜図１１を用いて説明する。
テープＢＧＡを製造するには、まず図４に示すような、片面に銅箔配線からなるリード１を形成すると共に貫通孔を形成したテープ基材２Ａと、図５に示すような、素子形成面の周辺部にＡｕのバンプ電極７を形成した半導体チップ３とを用意する。
上記テープ基材２Ａは、一端がリールに巻き取られた幅３５ｍｍの長尺テープであるが、図４にはＢＧＡ一個分の領域のみが示されている。このテープ基材２ＡのＢＧＡ一個分の領域の中央部には、半導体チップ３が配置される略正方形のデバイスホール８が形成され、リード１のそれぞれの一端部（インナーリード部１Ａ）が、このデバイスホール８の内側に延在している。また、リード１の中途部には、後の工程で半田バンプ６が接続されるランド部１Ｂが形成されている。これらのランド部１Ｂは、デバイスホール８の各辺に沿って２列に配置されている。ランド部１Ｂのさらに外側のテープ基材２Ａには、長方形の開孔９がランド部１Ｂを囲むように形成されている。これらの開孔９は、テープ基材２Ａを打ち抜く作業を容易にするためのもので、それらの内側のテープ基材２ＡがＢＧＡの配線基板２を構成するようになっている。
一方、半導体チップ３へのバンプ電極７の取り付けは、ワイヤボンディング装置を用いたボールボンディング方式で行う。
次に、図６に示すように、上記テープ基材２Ａのデバイスホール８に半導体チップ３を位置決めし、バンプ電極７と対応するリード１とを電気的に接続する。バンプ電極７とリード１とを接続するには、図７に示すように、ボンディングステージ１０の上に水平に載置した半導体チップ３のバンプ電極７にリード１のインナーリード部１Ａを重ね合わせ、上方から５００℃程度に加熱したボンディングツール１１を１秒程度圧着して、すべてのバンプ電極７と対応するインナーリード部１Ａとを同時に一括して接続する。
次に、上記テープ基材２Ａを図８に示すようなモールド金型に装着し、半導体チップ３が位置決めされたキャビティ１２の内部に樹脂を注入する。図示のように、このモールド金型は、上型１３Ａと下型１３Ｂとで構成されている。上型１３Ａの一部には突起部１４が設けられており、キャビティ１２に注入された樹脂は、この突起部１４の内側の部分が半導体チップ３を封止する封止樹脂４となり、外側の部分が補強枠５となる。また、上型１３Ａの一部に突起部１４を設けたことにより、半導体チップ３に近接した領域のテープ基材２Ａが突起部１４と下型１３Ｂとに挟まれて確実に固定される。これにより、キャビティ１２の内部に樹脂を注入した際に半導体チップ３が揺動し難くなるので、半導体チップ３の位置ずれに起因する成形不良率を低減することができる。
また、上記モールド金型は、上型１３Ａと下型１３Ｂのそれぞれに樹脂の注入口であるゲート１５が設けられている。これにより、半導体チップ３の主面側と裏面側とに樹脂が均一に流入されるので、樹脂の流入ばらつきに起因する成形不良率を低減することができる。
図９は、上記モールド金型を使ったトランスファ・モールド法によって樹脂４と補強枠５とを成形したテープ基材２Ａ（上面側）を示す平面図、図１０は、同じくテープ基材２Ａ（実装面側）を示す平面図である。
次に、上記テープ基材２Ａのランド部１Ｂに半田バンプ６を接続する。半田バンプ６をランド部１Ｂに接続するには、あらかじめボール状に成形しておいた半田バンプ６を図１１に示すようなボールマウンタ１６を使って真空吸引し、この状態でフラックス槽（図示せず）に半田バンプ６を浸漬してその表面にフラックスを塗布した後、フラックスの粘着力を利用して半田バンプ６を対応するランド部１Ｂに仮付けする。本実施形態では、ランド部１Ｂが形成された領域のテープ基材２Ａに補強枠５が設けられているので、この領域のテープ基材２Ａの反りや変形が防止されて平坦度が向上する。従って、多数の半田バンプ６を対応するランド部１Ｂに同時に押し付けた場合でも、すべての半田バンプ６がランド部１Ｂに確実に密着する。
その後、半田バンプ６を加熱リフローしてランド部１Ｂに固着した後、テープ基材２Ａの表面に残ったフラックス残渣を中性洗剤などを使って除去し、最後にテープ基材２Ａをチップ単位で打ち抜くことにより、前記図１〜図３に示すテープＢＧＡが完成する。このようにして得られたテープＢＧＡは、バーンイン／テスタによる検査に付されて良品と不良品とに選別された後、梱包、出荷される。
図１２は、上記テープＢＧＡと他の表面実装型パッケージ（例えばＱＦＰなど）とが実装されたプリント配線基板１８の平面図である。テープＢＧＡとＱＦＰは、テープＢＧＡの半田バンプ６およびＱＦＰのリード表面に塗布した半田ペースト（または半田メッキ）を加熱炉内でリフローすることにより、同時に一括して実装する。
このように、半導体チップ３を保護する封止樹脂４と、配線基板２０周辺部の平坦性を確保するための補強枠５とをトランスファ・モールド法によって同時に一括成形する本実施形態によれば、樹脂基板の周辺部に金属枠を接着した後、半導体チップをポッティング樹脂で封止する場合に比べて製造工程を低減することができ、かつ金属枠よりも安価なモールド樹脂で補強枠を形成することにより材料原価を低減することができるので、テープＢＧＡを安価に製造することができる。
また、ポッティング樹脂よりも耐湿性に優れたモールド樹脂で半導体チップを全面封止する本実施形態によれば、テープＢＧＡの信頼性を向上させることができる。
実施形態２
図１３は、本実施形態のテープＢＧＡを示す斜視図、図１４は、このテープＢＧＡの断面図である。
図示のように、本実施形態のテープＢＧＡは、半導体チップ３の裏面を封止樹脂４から露出させた構造になっている。このような構造は、特に消費電力の大きい半導体チップ３を搭載したテープＢＧＡの熱抵抗を低減するのに有効である。また、図１５に示すように、半導体チップ３の露出面に接着剤１７などを使って金属製の放熱フィン１９を接合することにより、テープＢＧＡの熱抵抗をさらに低減することができる。
半導体チップ３の裏面を封止樹脂４から露出させた上記テープＢＧＡを製造するには、まず前記実施の形態１の図８に示したモールド金型に比べて深さの浅いキャビティを備えたモールド金型を用意し、このモールド金型の上型に半導体チップ３の裏面が接触するようにテープ基材２Ａを装着した状態でキャビティに樹脂を注入し、封止樹脂４を成形すればよい。
実施形態３
図１６は、本実施形態のテープＢＧＡを示す斜視図、図１７は、このテープＢＧＡの断面図である。
図示のように、このテープＢＧＡの補強枠５およびその下部の配線基板２には、それらの上下面を貫通してリード１のランド部１Ｂに達する多数の貫通孔２０が設けられ、それぞれの貫通孔２０の内部には、導電材２１が埋め込まれている。導電材２１は、ランド部１Ｂに接続された半田バンプ６よりも高融点の半田や導電性ペーストなどで構成され、スクリーン印刷あるいは多点ノズルを備えたディスペンサによって貫通孔２０の内部に充填される。補強枠５に貫通孔２０を形成するには、図１８に示すように、上型１３Ａの一部に多数のピン２２を設けたモールド金型を使って補強枠５を成形する。
テープＢＧＡを上記のような構造とすることにより、図１９に示すように、複数のテープＢＧＡを基板実装面に対して垂直な方向に重ね合わせ、半田バンプ６と導電材２１とを介して共通のピン同士を電気的に接続したマルチチップ・モジュールを容易に実現することができる。この場合、半導体チップ３は、ＤＲＡＭなどのメモリＬＳＩを形成したものが使用される。
実施形態４
図２０は、本実施形態のテープＢＧＡを示す断面図である。図示のように、このテープＢＧＡは、配線基板２の下面側に補強枠５を設け、この補強枠５に形成された凹溝２３の内部に半田バンプ６を配置した構造になっている。補強枠５に凹溝２３を形成するには、図２１に示すように、下型１３Ｂの一部に多数の突起部２４を設けたモールド金型を使って補強枠５を成形する。
テープＢＧＡを上記のような構造とすることにより、図２２に示すように、ボールマウンタ１６を使って半田バンプ６をランド部１Ｂに仮付けする際、凹溝２３が半田バンプ６の位置決めガイドとして機能するので、半田バンプ６の仮付けを容易、かつ迅速に行うことができる。この場合も、補強枠５は、ランド部１Ｂが形成された領域のテープ基材２Ａの反りや変形を防止するように機能する。
以上、本発明者によってなされた発明を発明の実施形態に基づき具体的に説明したが、本発明は前記実施形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。
例えば図２３に示すように、封止樹脂４と補強枠５とを分離して成形してもよい。この場合は、封止樹脂４を成形するモールド金型のキャビティ（１２）と補強枠５を成形する上型（１３Ａ）の一部とに樹脂を直接供給するためのゲートをそれぞれ設ける必要がある。
産業上の利用可能性
半導体チップを封止する封止樹脂と配線基板の反りや変形を防ぐ補強枠とをトランスファ・モールド法で同時に樹脂成形する本発明のテープＢＧＡは、製造コストが安価で信頼性も高いことから、携帯情報機器、ディジタルカメラ、ノートパソコンといった小型軽量電子機器への実装に広く適用することができる。
【図面の簡単な説明】
図１、図２は、本発明の実施形態１である半導体装置の斜視図である。
図３は、本発明の実施形態１である半導体装置の斜視図である。
図４は、本発明の実施形態１である半導体装置の製造方法を示すテープ基材の平面図である。
図５は、本発明の実施形態１である半導体装置の製造方法を示す斜視図である。
図６は、本発明の実施形態１である半導体装置の製造方法を示す平面図である。
図７、図８は、本発明の実施形態１である半導体装置の製造方法を示す概略断面図である。
図９、図１０は、本発明の実施形態１である半導体装置の製造方法を示す平面図である。
図１１は、本発明の実施形態１である半導体装置の製造方法を示す概略断面図である。
図１２は、本発明の実施形態１である半導体装置を実装したプリント配線基板の平面図である。
図１３は、本発明の実施形態２である半導体装置の斜視図である。
図１４、図１５は、本発明の実施形態２である半導体装置の断面図である。
図１６は、本発明の実施形態３である半導体装置の斜視図である。
図１７は、本発明の実施形態３である半導体装置の断面図である。
図１８は、本発明の実施形態３である半導体装置の製造方法を示す概略断面図である。
図１９は、本発明の実施形態３である半導体装置を用いたマルチチップモジュールの断面図である。
図２０は、本発明の実施形態４である半導体装置の断面図である。
図２１、図２２は、本発明の実施形態４である半導体装置の製造方法を示す概略断面図である。
図２３は、本発明の他の実施形態である半導体装置の斜視図である。TECHNICAL FIELD The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a ball grid array (BGA) type semiconductor device in which a package substrate on which a semiconductor chip is mounted is mounted on a flint wiring substrate through solder bumps. It is related to effective technology.
Background Art A BGA in which a solder bump is attached to one surface of a package substrate on which a semiconductor chip is mounted and the package substrate is mounted on a printed wiring board via the solder bump is a QFP (Quad Flat Package) in which leads are drawn from the side surface of the package. Compared with SOP (Small Outline Package) or the like, there are advantages that the number of pins can be easily increased and the mounting area can be reduced.
Various structures have been proposed for the BGA, but a TCP (Tape Carrier) in which a package substrate is formed of an insulating tape as a BGA suitable for mounting on small and light electronic devices such as portable information devices, digital cameras, and notebook computers. Package) BGA (tape BGA) is known. This type of tape BGA is described in, for example, JP-A-7-32248, JP-A-8-88243, and JP-A-8-111433.
The inventor has also developed a BGA having the following structure (particularly, a fine pitch BGA with a narrow pitch of bumps). In this BGA, a device hole is formed in the central part of a resin wiring board having a plurality of leads made of Cu (copper) foil on one side, and a semiconductor chip is arranged there, and one end of the semiconductor chip and the lead Are electrically connected via Au bump electrodes, and the main surface of the semiconductor chip is sealed with a potting resin. Further, the other end of the lead extends to the peripheral portion of the wiring board to form a land portion, and a solder bump serving as an external connection terminal of the BGA is connected thereto.
Furthermore, as a reinforcing material for ensuring that the solder bumps can be positioned on the land portion in the process of assembling the BGA, a square frame-shaped metal frame is provided on the surface opposite to the solder bump bonding surface in the peripheral portion of the wiring board. Attached with an adhesive, the metal frame prevents the peripheral portion of the wiring board from warping.
However, the metal frame used in the above-mentioned BGA is obtained by punching a thin metal plate such as Cu (copper) with a press, applying an adhesive on one side, and further attaching a cover tape for protecting the adhesive on the surface. Therefore, the material is expensive, which increases the manufacturing cost of BGA. In addition, since a work of attaching a metal frame to the wiring board is required, the manufacturing process of the BGA increases. The work of attaching the metal frame is difficult to reduce costs by automation because the work of peeling the thin cover tape that protects the adhesive cannot be handled well by the robot hand.
The objective of this invention is providing the technique which can reduce the manufacturing cost of BGA (tape BGA, fine pitch BGA, etc.).
Another object of the present invention is to provide a technique capable of improving the reliability of a BGA (tape BGA, fine pitch BGA, etc.).
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
DISCLOSURE OF THE INVENTION The outline of representative ones of the inventions disclosed in the present application will be briefly described as follows.
The semiconductor device of the present invention includes a semiconductor chip, a wiring board provided so as to surround the semiconductor chip, a plurality of leads formed on the wiring board and having one end portion electrically connected to the semiconductor chip, A sealing resin covering the semiconductor chip; a plurality of bumps disposed along a peripheral portion of one surface of the wiring substrate and electrically connected to the other end portion of the lead; and the other surface of the wiring substrate And a resin-made reinforcing frame disposed so as to face the plurality of bumps with the wiring board interposed therebetween.
In addition, a semiconductor device of the present invention includes a semiconductor chip, a wiring board provided so as to surround the semiconductor chip, and a plurality of leads formed on the wiring board and having one end portion electrically connected to the semiconductor chip. And a sealing resin covering the semiconductor chip, a reinforcing frame provided along a peripheral portion of one surface of the wiring board, and a plurality of concave grooves formed in the reinforcing frame, A plurality of bumps electrically connected to the other end of the lead;
In addition, a semiconductor device of the present invention includes a semiconductor chip, a wiring board provided so as to surround the semiconductor chip, and a plurality of leads formed on the wiring board and having one end portion electrically connected to the semiconductor chip. A plurality of bumps disposed along a peripheral portion of one surface of the wiring board and electrically connected to the other end of the lead; and a sealing resin that covers the semiconductor chip; A resin reinforcing frame provided along the peripheral portion of the other surface and arranged to face the plurality of bumps across the wiring board, and the back surface of the semiconductor chip is sealed. Exposed from the stop resin.
Moreover, the manufacturing method of the semiconductor device of this invention includes the following processes.
(A) A semiconductor chip is disposed in the device hole of the tape base having a plurality of leads in which one end portion extends to the inside of the device hole and land portions for connecting bumps to other portions are formed. Electrically connecting the semiconductor chip and one end of the lead;
(B) forming a sealing resin covering the semiconductor chip and a reinforcing frame provided along a peripheral portion of one surface of the wiring board by a transfer mold method;
(C) connecting bumps to land portions of the plurality of leads, and arranging the bumps and the reinforcing frame so as to face each other with the wiring board interposed therebetween;
(D) The process of removing the unnecessary location of the said tape base material.
According to the present invention described above, the process of providing an expensive metal frame on the wiring board is not necessary, so that the material cost and the number of manufacturing steps can be reduced, and a low-cost BGA can be provided. Further, BGA with improved reliability can be provided by resin-sealing a semiconductor chip by a transfer molding method.
BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.
Embodiment 1
1 is a perspective view showing a tape BGA (fine pitch BGA) of this embodiment, FIG. 2 is a perspective view showing a mounting surface (solder bump mounting surface) of the tape BGA, and FIG. 3 is a cross section of the tape BGA. FIG.
The tape BGA of this embodiment includes a wiring board 2 made of polyimide resin having a plurality of leads 1 made of copper foil wiring on one side, a semiconductor chip 3 arranged in a device hole of the wiring board 2, and the semiconductor chip 3 And a plurality of solder bumps 6 attached along the peripheral portion of the wiring board 2 and the sealing resin 4 covering the wiring substrate 20, the rectangular frame-shaped reinforcing frame 5 provided along the peripheral portion of the wiring substrate 20. Yes.
A semiconductor chip 3 on which an LSI such as a microcomputer or ASIC is formed is electrically connected to one end portion (inner lead portion 1A) of the lead 1 through an Au bump electrode 7 provided on the peripheral portion of the main surface. ing. The other end of the lead 1 extends to the lower part of the reinforcing frame 5 provided in the peripheral part of the wiring board 2 and is electrically connected to the solder bump 6 in this region. One side of the wiring board 2 excluding the other end portion (land portion 1B) of the lead 1 to which the solder bump 6 is bonded is covered with a solder resist (not shown) for protecting the lead 1.
The reinforcing frame 5 provided in the peripheral portion of the wiring substrate 2, that is, the region where the solder bumps 6 are attached ensures the flatness of the peripheral portion of the wiring substrate 20, and the solder bumps 6 are attached in the solder bump 6 mounting step described later. It functions to be reliably joined to the land portion 1B. The reinforcing frame 5 is made of a synthetic resin molded by a transfer mold method.
The sealing resin 4 that protects the semiconductor chip 3 from the external environment is made of a synthetic resin that is molded by the transfer molding method in the same manner as the reinforcing frame 5 and covers the entire surface of the semiconductor chip 3. As shown in FIG. 1, the sealing resin 4 is connected to the reinforcing frame 5 at its four corners, and is molded integrally with the reinforcing frame 5.
As an example of the material and dimensions of each part of the tape BGA, the semiconductor chip 3 is made of single crystal silicon, and the dimensions are 7.6 mm × 7.6 mm and the thickness is 0.4 mm. The dimensions of the wiring board 2 made of polyimide resin are 15 mm × 15 mm and a thickness of 0.075 mm. The lead 1 is made of a copper foil wiring formed by etching an electrolytic copper foil (or rolled copper foil) having a thickness of 0.018 mm attached to one surface of the wiring board 2 and both ends thereof (inner lead portion 1A and The surface of the land 1B) is plated with Au / Ni.
The sealing resin 4 for sealing the semiconductor chip 3 and the reinforcing frame 5 formed integrally therewith are made of an epoxy resin filled with a filler such as silica. The dimensions of the sealing resin 4 are 14.6 mm × 14.6 mm and the thickness is 0.655 mm. The reinforcing frame 5 is formed only on one side of the wiring board 2 and has a thickness of 0.355 mm. The solder bump 7 joined to the land 1B of the lead 1 is made of an Sn (63%) / Pb (37%) alloy, and has a diameter of 0.3 mm and a pitch of 0.5 mm.
Next, a method for manufacturing the tape BGA of the present embodiment configured as described above will be described with reference to FIGS.
In order to manufacture the tape BGA, first, as shown in FIG. 4, a tape substrate 2A in which leads 1 made of copper foil wiring are formed on one side and through holes are formed, and an element formation surface as shown in FIG. And a semiconductor chip 3 having Au bump electrodes 7 formed on the periphery thereof.
The tape base material 2A is a long tape having a width of 35 mm, one end of which is wound on a reel. FIG. 4 shows only a region corresponding to one BGA. A substantially square device hole 8 in which the semiconductor chip 3 is arranged is formed in the central portion of the area of one BGA of the tape base 2A, and one end portion (inner lead portion 1A) of each lead 1 It extends inside the device hole 8. A land portion 1B to which the solder bump 6 is connected in a later process is formed in the middle portion of the lead 1. These land portions 1 </ b> B are arranged in two rows along each side of the device hole 8. A rectangular opening 9 is formed in the tape base 2A further outside the land 1B so as to surround the land 1B. These openings 9 are for facilitating the work of punching out the tape base material 2A, and the tape base material 2A on the inside constitutes a BGA wiring board 2.
On the other hand, the bump electrode 7 is attached to the semiconductor chip 3 by a ball bonding method using a wire bonding apparatus.
Next, as shown in FIG. 6, the semiconductor chip 3 is positioned in the device hole 8 of the tape base 2A, and the bump electrode 7 and the corresponding lead 1 are electrically connected. To connect the bump electrode 7 and the lead 1, as shown in FIG. 7, the inner lead portion 1A of the lead 1 is superimposed on the bump electrode 7 of the semiconductor chip 3 placed horizontally on the bonding stage 10, The bonding tool 11 heated to about 500 ° C. from above is pressure-bonded for about 1 second, and all the bump electrodes 7 and the corresponding inner lead portions 1A are simultaneously connected together.
Next, the tape base 2A is mounted on a mold as shown in FIG. 8, and a resin is injected into the cavity 12 where the semiconductor chip 3 is positioned. As shown in the figure, this mold is composed of an upper mold 13A and a lower mold 13B. A protrusion 14 is provided in a part of the upper mold 13A, and the resin injected into the cavity 12 becomes a sealing resin 4 for sealing the semiconductor chip 3 at the inner portion of the protrusion 14 and the outer portion The part becomes the reinforcing frame 5. Further, by providing the protrusion 14 on a part of the upper mold 13A, the tape base 2A in the region close to the semiconductor chip 3 is sandwiched between the protrusion 14 and the lower mold 13B and is securely fixed. As a result, the semiconductor chip 3 is less likely to swing when the resin is injected into the cavity 12, so that the molding defect rate due to the misalignment of the semiconductor chip 3 can be reduced.
In the mold, the upper mold 13A and the lower mold 13B are provided with gates 15 serving as resin injection ports. Thereby, since resin flows uniformly into the main surface side and the back surface side of the semiconductor chip 3, it is possible to reduce the molding defect rate due to the inflow variation of the resin.
FIG. 9 is a plan view showing a tape base 2A (upper surface side) in which the resin 4 and the reinforcing frame 5 are formed by the transfer molding method using the above mold, and FIG. 10 is also a tape base 2A (mounting). It is a top view which shows a surface side.
Next, the solder bump 6 is connected to the land portion 1B of the tape base 2A. In order to connect the solder bumps 6 to the land portion 1B, the solder bumps 6 formed in a ball shape in advance are vacuumed using a ball mounter 16 as shown in FIG. The solder bumps 6 are dipped and the flux is applied to the surface thereof, and then the solder bumps 6 are temporarily attached to the corresponding land portions 1B using the adhesive force of the flux. In this embodiment, since the reinforcing frame 5 is provided on the tape base material 2A in the region where the land portion 1B is formed, warping and deformation of the tape base material 2A in this region are prevented and the flatness is improved. Accordingly, even when a large number of solder bumps 6 are pressed against the corresponding land portions 1B at the same time, all the solder bumps 6 are securely adhered to the land portions 1B.
Thereafter, the solder bumps 6 are heated and reflowed to adhere to the land portion 1B, and then the flux residue remaining on the surface of the tape base 2A is removed using a neutral detergent. Finally, the tape base 2A is removed in units of chips. By punching, the tape BGA shown in FIGS. 1 to 3 is completed. The tape BGA thus obtained is subjected to an inspection by a burn-in / tester and sorted into a non-defective product and a defective product, and then packed and shipped.
FIG. 12 is a plan view of a printed wiring board 18 on which the tape BGA and another surface-mount package (for example, QFP) are mounted. The tapes BGA and QFP are simultaneously packaged by reflowing solder paste (or solder plating) applied to the solder bumps 6 of the tape BGA and the lead surface of the QFP in a heating furnace.
As described above, according to the present embodiment in which the sealing resin 4 for protecting the semiconductor chip 3 and the reinforcing frame 5 for ensuring the flatness of the periphery of the wiring substrate 20 are simultaneously formed by the transfer molding method. After bonding the metal frame to the periphery of the resin substrate, the manufacturing process can be reduced compared to the case where the semiconductor chip is sealed with potting resin, and the reinforcing frame is formed with a mold resin that is less expensive than the metal frame. Thus, the material cost can be reduced, and the tape BGA can be manufactured at low cost.
In addition, according to the present embodiment in which the entire surface of the semiconductor chip is sealed with a mold resin having higher moisture resistance than the potting resin, the reliability of the tape BGA can be improved.
Embodiment 2
FIG. 13 is a perspective view showing the tape BGA of this embodiment, and FIG. 14 is a cross-sectional view of the tape BGA.
As shown in the figure, the tape BGA of this embodiment has a structure in which the back surface of the semiconductor chip 3 is exposed from the sealing resin 4. Such a structure is particularly effective in reducing the thermal resistance of the tape BGA on which the semiconductor chip 3 with high power consumption is mounted. Further, as shown in FIG. 15, the thermal resistance of the tape BGA can be further reduced by bonding the metal heat dissipating fins 19 to the exposed surface of the semiconductor chip 3 using an adhesive 17 or the like.
In order to manufacture the tape BGA in which the back surface of the semiconductor chip 3 is exposed from the sealing resin 4, first, a mold having a cavity having a shallower depth than that of the mold shown in FIG. A mold is prepared, and the sealing resin 4 is molded by injecting a resin into the cavity with the tape base 2A mounted so that the back surface of the semiconductor chip 3 contacts the upper mold of the mold.
Embodiment 3
FIG. 16 is a perspective view showing the tape BGA of this embodiment, and FIG. 17 is a cross-sectional view of the tape BGA.
As shown in the figure, the reinforcing frame 5 of the tape BGA and the wiring substrate 2 below the tape BGA are provided with a plurality of through holes 20 that penetrate the upper and lower surfaces of the tape BGA and reach the land portion 1B of the lead 1. A conductive material 21 is embedded in the hole 20. The conductive material 21 is made of solder or conductive paste having a melting point higher than that of the solder bump 6 connected to the land portion 1B, and is filled into the through hole 20 by screen printing or a dispenser equipped with a multipoint nozzle. . In order to form the through holes 20 in the reinforcing frame 5, as shown in FIG. 18, the reinforcing frame 5 is formed using a mold die in which a large number of pins 22 are provided in a part of the upper mold 13A.
By forming the tape BGA as described above, as shown in FIG. 19, a plurality of tape BGAs are superposed in a direction perpendicular to the substrate mounting surface, and are shared via the solder bumps 6 and the conductive material 21. A multichip module in which the pins are electrically connected can be easily realized. In this case, the semiconductor chip 3 formed with a memory LSI such as a DRAM is used.
Embodiment 4
FIG. 20 is a cross-sectional view showing the tape BGA of this embodiment. As shown in the figure, this tape BGA has a structure in which a reinforcing frame 5 is provided on the lower surface side of the wiring board 2 and solder bumps 6 are arranged inside a groove 23 formed in the reinforcing frame 5. In order to form the concave groove 23 in the reinforcing frame 5, as shown in FIG. 21, the reinforcing frame 5 is formed by using a mold having a large number of protrusions 24 provided on a part of the lower mold 13B.
When the tape BGA is structured as described above, as shown in FIG. 22, when the solder bump 6 is temporarily attached to the land portion 1B using the ball mounter 16, the groove 23 serves as a positioning guide for the solder bump 6. Since it functions, the solder bumps 6 can be easily and quickly attached. Also in this case, the reinforcing frame 5 functions to prevent warping or deformation of the tape base material 2A in the region where the land portion 1B is formed.
Although the invention made by the present inventor has been specifically described based on the embodiments of the invention, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.
For example, as shown in FIG. 23, the sealing resin 4 and the reinforcing frame 5 may be formed separately. In this case, it is necessary to provide gates for directly supplying the resin to the cavity (12) of the mold for molding the sealing resin 4 and a part of the upper mold (13A) for molding the reinforcing frame 5. .
INDUSTRIAL APPLICABILITY The tape BGA of the present invention in which a sealing resin for sealing a semiconductor chip and a reinforcing frame for preventing warping and deformation of a wiring board are simultaneously molded by a transfer molding method is inexpensive and reliable. Because of its high performance, it can be widely applied to small and light electronic devices such as portable information devices, digital cameras, and notebook computers.
[Brief description of the drawings]
1 and 2 are perspective views of a semiconductor device according to Embodiment 1 of the present invention.
FIG. 3 is a perspective view of the semiconductor device according to the first embodiment of the present invention.
FIG. 4 is a plan view of the tape base material illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
FIG. 5 is a perspective view showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
FIG. 6 is a plan view showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
7 and 8 are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention.
9 and 10 are plan views showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
FIG. 11 is a schematic cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
FIG. 12 is a plan view of a printed wiring board on which the semiconductor device according to the first embodiment of the present invention is mounted.
FIG. 13 is a perspective view of a semiconductor device according to the second embodiment of the present invention.
14 and 15 are cross-sectional views of the semiconductor device according to the second embodiment of the present invention.
FIG. 16 is a perspective view of a semiconductor device according to Embodiment 3 of the present invention.
FIG. 17 is a cross-sectional view of a semiconductor device according to Embodiment 3 of the present invention.
FIG. 18 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 3 of the present invention.
FIG. 19 is a cross-sectional view of a multichip module using the semiconductor device according to the third embodiment of the present invention.
FIG. 20 is a cross-sectional view of a semiconductor device according to Embodiment 4 of the present invention.
21 and 22 are schematic sectional views showing a method for manufacturing a semiconductor device according to the fourth embodiment of the present invention.
FIG. 23 is a perspective view of a semiconductor device according to another embodiment of the present invention.

Claims (3)

半導体チップを封止する封止樹脂と、前記封止樹脂の周囲を囲む補強枠とを有する半導体装置の製造方法であって、
（ａ）主面に複数の電極が形成された半導体チップを用意する工程、
（ｂ）デバイスホールと、一端部が前記デバイスホールの内側に延在し、他端部の一部にバンプを接続するためのランド部を有する複数のリードとが形成されたテープ基材を用意する工程、
（ｃ）前記半導体チップを前記テープ基材の前記デバイスホールに配置し、前記半導体チップと前記リードの一端部とを電気的に接続する工程、
（ｄ）前記封止樹脂が形成される領域と前記補強枠が形成される領域の間の前記テープ基材の一部を上型の突起部と下型とで挟んで固定し、トランスファモールド法によって、前記封止樹脂と前記補強枠とを一体に成形する工程、
を含むことを特徴とする半導体装置の製造方法。A manufacturing method of a semiconductor device having a sealing resin for sealing a semiconductor chip, and a reinforcing frame surrounding the periphery of the sealing resin,
(A) preparing a semiconductor chip in which a plurality of electrodes are formed on the main surface;
(B) A tape base material in which a device hole and a plurality of leads having one end portion extending inside the device hole and a land portion for connecting a bump to a part of the other end portion is prepared. The process of
(C) arranging the semiconductor chip in the device hole of the tape base material and electrically connecting the semiconductor chip and one end of the lead;
(D) A part of the tape base between the region where the sealing resin is formed and the region where the reinforcing frame is formed is fixed by sandwiching it between the upper mold protrusion and the lower mold. The step of integrally molding the sealing resin and the reinforcing frame ,
A method for manufacturing a semiconductor device, comprising: 前記工程（ｄ）の後、前記テープ基材の不要箇所を除去する工程をさらに含む請求項１記載の半導体装置の製造方法。  The method of manufacturing a semiconductor device according to claim 1, further comprising a step of removing unnecessary portions of the tape base material after the step (d). 前記複数のリードのランド部にバンプを接続する工程をさらに含む請求項１記載の半導体装置の製造方法。  The method for manufacturing a semiconductor device according to claim 1, further comprising a step of connecting bumps to land portions of the plurality of leads.
JP2000546392A 1998-04-24 1998-04-24 Manufacturing method of semiconductor device Expired - Fee Related JP4038021B2 (en)

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