JPH1155694A - Image comparison device - Google Patents

Abstract

(57) [Summary] [Problem] There is a disadvantage that synchronization between image signals cannot be achieved with an accuracy higher than the sampling clock, and frame delay correction and line shift cannot be corrected. An image comparison apparatus that compares an original image signal before input of a digital processing circuit with an output image signal and measures the degree of image quality deterioration due to the digital processing circuit and the like. In addition to adding the included marker signal to the original image signal, a sampling clock circuit and a phase variable circuit for the reproduced image are provided so that the phase can be adjusted so that the difference value between the original image signal and the reproduced image signal is minimized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CODEC device or the like by comparing an output image via a CODEC device or a digital network (hereinafter collectively referred to as a digital processing circuit system) with an input original image. The present invention relates to an image comparison device that measures and evaluates image quality deterioration and noise generation amount due to image quality.

[0002]

2. Description of the Related Art A digital processing circuit device such as a CODEC device having an encoder section and a decoder section and performing compression encoding and decompression decoding of an image signal is used. CODE
In order to compare and calculate the output image of the C apparatus and the input original image in the image comparison apparatus and to evaluate the output image correctly, it is necessary to exactly match the phase of the delayed output image with the phase of the input original image. However, the conventional image comparison device has a configuration in which a sampling clock of an image signal is generated based only on the input synchronization signal.

[0003]

For this reason, there has been a drawback that synchronization between image signals cannot be achieved with an accuracy higher than the sampling clock and frame delay correction and line shift correction cannot be performed. Further, in a CODEC device or the like, the image signal and the synchronization signal are separated after input, and the synchronization signal is added at the time of output after processing only the image signal, so that the distortion of the image signal itself and the error of the circuit system are not corrected. there were.

[0004]

SUMMARY OF THE INVENTION The present invention compares an output image signal output via a digital processing circuit such as a digital network with an original image signal before being input to the digital processing circuit. Thus, in an image comparison apparatus that measures the degree of image quality deterioration due to the digital circuit system, a marker signal including a horizontal phase detection waveform and a frame number is added to an original image signal, and a sampling clock circuit for a reproduced image is used. It is characterized in that a phase variable circuit is provided and the phase can be adjusted so that the difference value between the original image signal and the reproduced image signal is minimized.

[0005]

FIG. 1 is a block diagram showing a configuration example of an image comparison apparatus. A marker signal required for image comparison is superimposed on the original image signal applied to the input terminal 1 by a marker adding circuit 2. As shown in FIG. 2, a different signal is added to the marker signal for each frame of the original image signal. The marker signal is composed of a frame number part for detecting a frame number and a horizontal phase detection waveform part. In the present embodiment, a sine waveform is used as the horizontal phase detection waveform, but another waveform such as a rectangular wave may be used.

One of the original image signals on which the marker signal is superimposed is output to the outside as it is, and is again input to the apparatus as a reproduced image signal via a digital processing circuit system 9 such as a CODEC device or a network. The original image signal on which the marker signal is superimposed is also input to the AD converter 5 and, at the same time, is also applied to the sync separation circuit 3. The AD converter 5 operates on the basis of the synchronization signal output from the synchronization separation circuit 3, converts the original image signal on which the marker signal is superimposed with the clock from the sampling clock circuit 4 into digital data, and converts it into original image data. Add to delay memory 6.

The delay memory 6 is composed of a large-capacity semiconductor memory, and includes a circuit for sequentially writing original image data from the AD converter 5 and a read circuit for reading data from an arbitrary address and transferring the data to the frame memory 7. Have been. That is, when the image data for one frame is 512 kbytes, data is sequentially written from address 0, and
If data is sequentially read from the k-th address, the signal can be delayed by a time corresponding to one frame. Actually, the delay time can be read from an arbitrary address, and the delay time can be set for each pixel. The read address for determining the delay amount is set by the delay amount setting unit 8.

The initial setting of the delay amount is zero. This delay amount is calculated from the frame number included in the marker signal of the reproduced image signal. For example, if the frame number is 0
If the frame number of the reproduced image is 10, assuming that the frame numbers are repeatedly assigned to from 63 to 63, the read address of the delay memory 6 is read every address 0 to 512k, and the marker signal is extracted to make the frame number 10 Find the address and use it as the amount of delay. At this time,
When the marker signal of the reproduced image signal deviates from the original image signal in the line direction, the correction is performed by changing the start position of capturing the reproduced image signal.

The reproduced image signal, which becomes the signal to be measured through the digital processing circuit system 9, is input to the sync separation circuit 10 and at the same time to the AD converter 14. The clock signal generated by the sampling clock circuit 11 based on the synchronization signal from the synchronization separation circuit 10
It is supplied to the converter 14. The reproduced image data output from the AD converter 14 is stored in the frame memory 15. The reproduced image data is compared with the original image data stored in the frame memory 7 by software in the CPU 16 by software.

The CPU 16 controls the correction circuit 13 so that the energy difference value of the horizontal phase detection waveform portion in the marker signal between the original image data and the reproduced image data is minimized, and the phase variable circuit 12 performs coarse adjustment in pixel units. After that, the clock phase is further changed within one pixel, and the reproduced image signal is digitized at the same timing as the original image signal to obtain reproduced image data, so that a highly accurate image comparison operation can be performed. In addition,
The marker signal is generated with a signal component of 1 MHz or less in consideration of an SIF format such as MPEG1.

[0011]

According to the present invention, the accuracy of comparison between two images is improved, and the state of deterioration of image quality, noise and the like can be measured accurately and in real time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a waveform chart showing an embodiment of a marker signal.

[Explanation of symbols]

 2 Marker addition circuit 9 Digital processing circuit system 11 Sampling clock circuit 12 Phase variable circuit

Claims (1)

[Claims] An image output by a digital processing circuit system such as a digital network is compared with an original image signal before being input to the digital processing circuit system to obtain image quality by the digital circuit system. In an image comparison apparatus for measuring the degree of deterioration of the original image, a marker signal including a horizontal phase detection waveform and a frame number is added to an original image signal, and a sampling clock circuit and a phase variable circuit for a reproduced image are provided. An image comparison device, wherein a phase can be adjusted so that a difference value between a signal and a reproduced image signal is minimized.