JP2000236487A - Image processing device - Google Patents

Abstract

(57) [Object] To provide an image processing apparatus and an image processing method capable of accurately converting an analog video signal into a digital video signal despite being inexpensive. A CCD camera for outputting a captured image as an analog video signal and outputting a pixel clock signal synchronized with each pixel of the image; a delay element for delaying the pixel clock signal from the CCD camera; ,
An A / D converter 12 for converting an analog video signal from the CCD camera into a digital video signal by sampling the analog video signal from the CCD camera using the pixel clock signal delayed by the delay element as a sampling clock.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus and an image processing method for generating image data from a video signal from a camera, and more particularly to a technique for obtaining image data accurately reproducing an image captured by a camera.

[0002]

2. Description of the Related Art Conventionally, solid-state imaging device cameras (hereinafter referred to as "C
2. Description of the Related Art There is known an image processing apparatus that digitizes an analog video signal obtained by photographing with a “CD camera” and stores the digitalized image signal as image data. The CCD camera used in this image processing apparatus generates and outputs a video signal as follows.

Now, consider a case where a point light source is photographed. In the case of an ideal point light source, if a CCD device that receives light from the light source is scanned in the horizontal direction, only a portion corresponding to one pixel should output a significant signal. However, since the light actually spreads on the imaging surface of the CCD element, the brightness with respect to the horizontal position of the imaging surface is, as shown in FIG.
4 shows a smooth Gaussian distribution having a peak at a position corresponding to a point light source. Light from such a point light source irradiates a CCD element built in a CCD camera, thereby producing a CC image.
The D element outputs a digitized signal as shown in FIG. 6 as a pixel signal.

The CCD camera outputs a pixel signal from the CCD element as a video signal from the CCD camera and outputs a pixel clock signal indicating a temporal position of the pixel. The pixel clock signals are represented by a1, a2,
As shown by a3, a4,..., the signal has a rising or falling change between a certain pixel signal and the next pixel signal.

In an image processing apparatus, image data is generated by A / D converting an image signal from such a CCD camera with an A / D converter. In this A / D conversion, a pixel clock signal from the CCD camera or a clock signal of the A / D converter itself is used as a sampling clock.

[0006]

However, the above-mentioned CCD
When a pixel signal from the element is output as a video signal as it is, a video signal which causes interference with the pixel signal and a pixel clock signal and other signals in the CCD camera and is superimposed with high frequency noise is output. Therefore, the CCD camera
A signal from which high-frequency noise has been removed via a low-pass filter is output as a video signal.

The video signal from the CCD camera is A / A
Since noise may be superimposed before reaching the D converter, a low-pass filter may be provided immediately before the A / D converter in some cases. In these cases, according to the sampling theorem, the low-pass filter needs to have a characteristic of blocking a signal having a frequency equal to or more than の of the sampling frequency. However, it is difficult to construct an ideal low-pass filter that blocks all signals having a frequency equal to or more than の of the sampling frequency.

As described above, in the conventional image processing apparatus, A
Since a non-ideal low-pass filter is provided on the input side of the / D converter, a video signal including aliasing distortion is input to the A / D converter as shown by the thick line in FIG. As a result, there is a problem that the image processing apparatus cannot accurately convert an analog video signal into a digital signal. In this case, a value different from the true value is obtained depending on the sampling position.
There is a problem that an error increases when accuracy of a pixel or less is required.

Further, as in the audio field, by sampling at a high frequency, performing A / D conversion, and then performing low-pass filter processing by digital signal processing, an analog video signal is accurately converted into a digital signal. It is also possible to do. However, this method requires an A / D converter that performs sampling at a high frequency, and has a problem that the cost of the image processing apparatus increases.

The present invention has been made to solve such a problem, and an image processing apparatus and an image processing method capable of accurately converting an analog video signal into a digital video signal despite being inexpensive. The aim is to provide a method.

[0011]

In order to achieve the above object, an image processing apparatus according to a first aspect of the present invention outputs a captured image as an analog video signal and synchronizes the image with each pixel of the image. Imaging means for outputting a pixel clock signal, a delay means for delaying the pixel clock signal from the imaging means, and an analog video signal from the imaging means using the pixel clock signal delayed by the delay means as a sampling clock. A / D conversion means for converting the digital video signal into a digital video signal by sampling the digital video signal. In this case, the delay unit can be configured to include a delay time adjusting unit that changes a delay time.

Further, the image processing apparatus according to the first aspect further comprises an image memory for storing the digital video signal from the A / D conversion means as image data, wherein the imaging means comprises a vertical synchronizing signal and Further output horizontal sync signal,
The image memory may be configured to store the image data from the A / D converter in correspondence with the vertical synchronization output and the horizontal synchronization output.

In this case, recognition means for recognizing the waveform of the analog video signal from the image pickup means based on the image data from the image memory, and a delay amount of the delay means are determined according to the recognition result by the recognition means. And control means for performing the control.

The image processing method according to the second aspect of the present invention outputs a captured image as an analog video signal and outputs a pixel clock signal synchronized with each pixel of the image for the same purpose as described above. A first step of outputting, a second step of delaying the pixel clock signal, and a third step of converting the analog video signal into a digital video signal by sampling the analog video signal using the delayed pixel clock signal as a sampling clock , And.

In the image processing method according to the second aspect,
The method further includes the step of recognizing the waveform of the analog video signal based on the digital video signal obtained by the conversion in the third step, and the step of determining the delay amount in the second step according to the recognition result. Can be configured.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of an image processing apparatus according to Embodiment 1 of the present invention. This image processing apparatus includes a CCD camera 10, a delay element 11, an A / D converter 12, a control circuit 13, an image memory 14, and a central processing unit (CPU) 15.

The CCD camera 10 is the same as the CCD camera described in the section of the prior art. That is, the CCD camera 1
Numeral 0 outputs a pixel signal from a CCD element incorporated in the CCD camera 10 as a video signal from the CCD camera, and outputs a pixel clock signal indicating a temporal position of the pixel. The pixel clock signals are a1, a2, a in FIG.
3, a4,..., That is, a signal having a rising or falling change at the boundary between a certain pixel signal and the next pixel signal.

The CCD camera 10 generates a horizontal synchronizing signal and a vertical synchronizing signal and supplies them to the control circuit 13. These horizontal synchronizing signal and vertical synchronizing signal are used to specify a recording position when an image for one screen is stored in the image memory.

The delay element 11 delays the pixel clock signal from the CCD camera 10. The delayed image device clock signal is supplied to a clock input terminal of the A / D converter 12. Note that the 1 sent from the CCD camera 10
The width of the pixel is about 70 nanoseconds and the sampling time is about 5 nanoseconds.

The delay element 11 includes a first delay element and a second delay element.
And a delay element. Each delay element is constituted by, for example, an inductance element. The first delay element is
Signals input to the input terminals are 0, 10, 20, 30,
It has eight output terminals for delaying and outputting at intervals of 10 nanoseconds such as 40, 50, 60, and 70 nanoseconds. Similarly, the second delay element converts the signal input to the input terminal into
It has eight output terminals for delaying and outputting at intervals of 3 nanoseconds such as 0, 3, 6, 9, 12, 15, 18, and 21 nanoseconds.

The first delay element and the second delay element are serially connected. That is, the input terminal of the first delay element is connected to the CCD camera 10 so that an image clock signal is supplied. Any output terminal of the first delay element is connected to an input terminal of the second delay element, and any output terminal of the second delay element is connected to a clock input terminal of the A / D converter 12. According to this configuration,
By appropriately selecting and connecting the output terminals of the first delay element and the second delay element, the delay time can be finely changed.

The A / D converter 12 samples the analog video signal from the CCD camera 10 using the signal from the delay element 11 as a sampling clock and converts it into a digital video signal. The digital video signal from the A / D converter 12 is supplied to the pixel memory 14. Control circuit 13
Generates a write address for the pixel memory 14 based on a vertical synchronization signal, a horizontal synchronization signal, and a pixel clock signal from the CCD camera 10. This control circuit 13
Is supplied to the image memory 14.

A digital video signal from the A / D converter 12 is written in the image memory 14 in accordance with a write address from the control circuit 13. The image memory 14 can be read from the CPU 15. C
The PU 15 reads out the image data from the image memory 14 and uses it for various image processing, for example, recognition processing of the surrounding environment.

The operation of the image processing apparatus configured as described above will be described. First, when photographing is performed by the CCD camera 10, the CCD camera 10 outputs an analog video signal, a pixel clock signal, a vertical synchronization signal, and a horizontal synchronization signal. The analog video signal is sent to the A / D converter 12.
The pixel clock signal is sent to the delay element 11 and the control circuit 13,
The vertical synchronization signal and the horizontal synchronization signal are supplied to the control circuit 13, respectively.

The pixel clock signal is delayed by the delay element 11 and is used as a sampling clock by the A / D converter 12.
Supplied to Therefore, by appropriately changing the delay time of the delay element 11, the sampling position of the analog video signal can be moved back and forth.

Here, the setting of the delay time in the delay element 11 is performed as follows. For example, the point light source is CCD
While viewing the distorted analog video signal obtained by shooting with the camera 10 as shown by the bold line in FIG. 3 and the digital video signal output from the A / D converter 12, the peak position of the analog video signal (see FIG. b1) so that the digital video signal output from the A / D converter 12 has the maximum value.
The connection state of the delay element and the second delay element is changed.

As a result, in the A / D converter 12, b
Since sampling is performed at the timings of 1, b2, b3, b4,..., The analog video signal from the CCD camera 10 is sampled at an optimum position for reproducing the original pixel signal. The pixel clock signal delayed by the delay element 11 in this manner is supplied to the A / D converter 12
Supplied to Then, the A / D converter 12 samples the analog video signal from the CCD camera 10 using the delayed image clock signal from the delay element 11 to generate a digital video signal. This digital video signal is supplied to the image memory 14.

On the other hand, the control circuit 13 includes the CCD camera 10
To generate an address on the image memory 14 corresponding to the position of the image determined by the vertical synchronization signal and the horizontal synchronization signal. Then, the generated address is output as a write address in synchronization with a pixel clock signal from the CCD camera 10. Thus, the digital video signal from the A / D converter 12 is written to the image memory 14.
The CPU 15 reads out the digital video signal stored in the image memory 14 and performs various image processing.

As described above, according to the first embodiment, the analog video signal from the CCD camera 10 can be sampled at an optimum position by appropriately delaying the pixel clock signal from the CCD camera 10. As a result, the original pixel signal can be accurately reproduced. In addition, since the analog video signal can be sampled at an optimum position, even if a low-pass filter having low blocking performance is used as the low-pass filter, it is possible to remove the influence of aliasing distortion. Alternatively, the effect of aliasing distortion can be removed without using any low-pass filter.

Next, an image processing apparatus according to Embodiment 2 of the present invention will be described. FIG. 2 is a block diagram illustrating a configuration of an image processing apparatus according to Embodiment 2 of the present invention. In this image processing apparatus, the amount of delay of the delay element 11 in the first embodiment can be set by a control signal from the CPU 15. Therefore, the delay element 1
1 is different from the block diagram shown in FIG. 1 in that a control signal is supplied to the block 1.

Delay element 11 according to the second embodiment
As shown in FIG. 4, the delay element 11 includes a first delay element 20, a second delay element 21, a first selector 22, and a second selector 23. The first delay element 20 and the second delay element 20 are the same as the first delay element and the second delay element used in the first embodiment, respectively. First
The selector 22 and the second selector 23 select and output one signal from eight input signals.

The input terminal of the first delay element 20 has C
A pixel clock signal from the CD camera 10 is input.
Each of the eight output terminals of the first delay element 20
It is connected to eight input terminals of the first selector 22.
The output terminal of the first selector 22 is connected to the second delay element 21.
Is connected to the input terminal of A control signal from the CPU 15 is input to a control input terminal of the first selector 22.

Each of the eight output terminals of the second delay element 21 is connected to eight input terminals of the second selector 23. The output terminal of the second selector 22 is A /
It is connected to the clock input terminal of the D converter 12. A control signal from the CPU 15 is input to a control input terminal of the second selector 23.

The operation of setting the delay amount for the delay element 11 in this image processing apparatus in the above configuration will be described. The setting of the delay amount is performed while the CCD camera 10 captures an image of a point light source. First, the CPU 15 sends a control signal for selecting the 0 ns delay time of the first delay element 20 and the 0 ns delay time of the second delay element 21 to the first selector 22 and the second selector 23. Supply to each control input terminal. In this state, the analog video signal from the CCD camera 10 is converted into a digital video signal by the A / D converter 12 and stored in the image memory 14.

Next, the CPU 15 operates the image memory 14.
Is searched for and stored in a predetermined memory (not shown), and the output terminal of the first delay element 20 and the output terminal of the second delay element 21 which are selected at that time are retrieved. The delay amount data is stored in the memory.

Next, a control signal for selecting a delay time of 0 nanosecond of the first delay element 20 and a delay time of 3 nanosecond of the second delay element 21 is supplied to the first selector 22 and the second selector 23. To each control input terminal. Then, similarly to the above, the maximum value of the image data stored in the image memory 14 is retrieved and stored in the memory, and the output terminal of the first delay element 20 selected at that time and the second
The delay amount data representing the output terminal of the delay element 21 is stored in the memory. Hereinafter, a control signal is generated such that the output terminals of the first delay element 20 and the second delay element 21 are sequentially selected, and the same operation as described above is repeated.

When the maximum value and the delay amount data are obtained for all the combinations of the output terminals of the first delay element 20 and the second delay element 21, the largest value among the obtained maximum values is searched. The delay amount data corresponding to the searched maximum value is extracted. Then, based on the delay amount data, the output terminal of the first delay element 20 and the second delay element 21
A control signal for selecting the output terminal is generated and supplied to the first selector 22 and the second selector 23.

As a result, the amount of delay in the delay element 11 is determined, and the A / D converter 12 is set to sample at the peak value of the analog video signal from the CCD camera 10. Therefore, as in the first embodiment, C
Since the optimal position for sampling the analog video signal from the CD camera 10 is determined, the original pixel signal can be accurately reproduced. According to the second embodiment, since it is not necessary to manually set the delay amount, the image processing apparatus can be set to an optimum state in a short time.

[0040]

As described in detail above, according to the present invention,
It is possible to provide an image processing apparatus and an image processing method that can accurately convert an analog video signal into a digital video signal despite being inexpensive.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image processing apparatus according to Embodiment 1 of the present invention.

FIG. 2 is a block diagram illustrating a configuration of an image processing apparatus according to Embodiment 2 of the present invention.

FIG. 3 is a diagram for explaining the operation of the image processing apparatus according to the present invention in comparison with a conventional image processing apparatus.

FIG. 4 is a block diagram showing a configuration of a delay element in an image processing device according to Embodiment 2 of the present invention.

FIG. 5 is a diagram illustrating a distribution of brightness on an imaging surface of a point light source.

6 is a diagram for explaining a pixel signal obtained in the state shown in FIG.

[Explanation of symbols]

 Reference Signs List 10 CCD camera 11 Delay element 12 A / D converter 13 Control circuit 14 Image memory 15 CPU 20 First delay element 21 Second delay element 22 First selector 23 Second selector

Claims (6)

[Claims] 1. An imaging means for outputting a captured image as an analog video signal and outputting a pixel clock signal synchronized with each pixel of the image, a delay means for delaying a pixel clock signal from the imaging means, A / D conversion means for converting an analog video signal from the imaging means into a digital video signal by sampling the analog video signal from the imaging means using the pixel clock signal delayed by the delay means as a sampling clock. 2. The image processing apparatus according to claim 1, wherein said delay means has a delay time adjusting means for changing a delay time. 3. An image memory for storing a digital video signal from the A / D conversion means as image data, wherein the imaging means further outputs a vertical synchronizing signal and a horizontal synchronizing signal. 2. The image processing apparatus according to claim 1, wherein the image data from the A / D converter is stored in correspondence with the vertical synchronization output and the horizontal synchronization output. 4. A recognizing means for recognizing a waveform of an analog video signal from said imaging means based on image data from said image memory, and a delay amount of said delay means is determined according to a recognition result by said recognizing means. The image processing apparatus according to claim 3, further comprising: a control unit. 5. A first step of outputting a photographed image as an analog video signal and outputting a pixel clock signal synchronized with each pixel of the image; a second step of delaying the pixel clock signal; A third step of converting the analog video signal into a digital video signal by sampling the analog video signal using the pixel clock signal as a sampling clock;
An image processing method comprising: 6. A step of recognizing a waveform of the analog video signal based on the digital video signal obtained by the conversion in the third step, and a step of determining a delay amount in the second step according to the recognition result. The image processing method according to claim 5, further comprising: