JPH1145839A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor chip and its manufacturing method, wherein improvement of yield of semiconductor products after chip mounting is markedly facilitated, as compared with the conventional technique by facilitating so as to relate manufacturing process record, i.e., manufacturing data of the respective semiconductor chips with characteristics data. SOLUTION: Effective information for defining chip positions on a wafer 1,e. g. chip position designation marks as numbers specific to chip regions 2 is imparted to respective semiconductor chips 3. The effective information for defining chip positions on the wafer (which are also called chip position designation information here in after) means information useful for deciding space positions on the wafer of specified chip regions, before being divided into semiconductor chips. As a result, the examination and analysis of relation between failures or irregularity of characteristics for semiconductor products after chip mounting and chip positions on a wafer are facilitated, and improvement in manufacturing processes for increasing the yield of semiconductor products after the chip mounting has been conducted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip and a method for manufacturing the same.

[0002]

2. Description of the Related Art In a semiconductor manufacturing process, a circuit function is formed in each of a large number of chip areas divided on a main surface of a wafer, and thereafter, a wafer process in which a wafer is diced and divided into chips is divided into a wafer process and a wafer process. In general, a characteristic inspection, an appearance inspection, and the like are performed at least at each stage before chip division, after chip division, and after mounting. In the case of inspecting before chip division, some defective mark is given to the chip area where the inspection result is defective. Thus, after chip division, chips having defective marks are separated and eliminated.

[0003]

However, in spite of the fact that defective chips are removed before being divided and mounted, there are many cases in which the cause of failure of a semiconductor product after chip mounting is the semiconductor chip itself. In this case, since the semiconductor chip cannot be specified after the chip is mounted, it is difficult to analyze the relationship between the characteristics of the semiconductor chip itself, the manufacturing process, and the like, and the defect item of the semiconductor product. In semiconductor products, it is important to improve the yield of semiconductor products after chip mounting, and the cause and improvement of defective items are continually investigated.However, this is an obstacle to improving the yield by investigating and improving the cause of defective items. Had become.

[0004] In addition, in the case of improving the characteristics of a manufactured semiconductor chip or improving a manufacturing process, it is necessary to perform the test based on test data of a semiconductor product after chip mounting. , It is difficult to identify the manufacturing process history given to each semiconductor chip,
A sufficient effect could not be obtained. SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has made it easy to associate the manufacturing process history of each semiconductor chip, that is, the manufacturing data with the characteristic data of the semiconductor chip, and to increase the yield of semiconductor products after chip mounting. It is an object of the present invention to provide a semiconductor chip and a method of manufacturing the same, which can be much easier to improve.

[0005]

According to the structure described in claim 1 or 4, information effective for specifying the chip position on the wafer is given to each semiconductor chip. here,
Information useful for specifying a chip position on a wafer (hereinafter, also referred to as chip position designation information) is information useful for determining a spatial position on a wafer of a predetermined chip area before being divided into semiconductor chips. means.

It is well known that each chip area is arranged in the same arrangement pattern on each wafer flowing in the same process line. Therefore, each chip area
By having information about its position on the wafer,
Even after chip division, since the chip position of each semiconductor chip on the original wafer can be known, the defect and characteristic variation of the semiconductor product after mounting and the characteristics of the semiconductor chip and the chip position on the wafer can be compared. Investigate and analyze relationships easily. Therefore, it becomes easy to narrow down the inspection standards of the semiconductor chip characteristics and to clarify the cause in the manufacturing process for improving the yield of the semiconductor product after mounting.

As the chip position designation information, different chip numbers and chip codes assigned to respective chip regions on the wafer are preferable, but in order to reduce the number of numbers and codes, a plurality of chip numbers and codes on the same wafer are required. It is also possible to assign the same number or code to the chip areas of the above. For example, each chip area may be grouped into a plurality of chip areas adjacent to each other, and a number or a code may be assigned to each group. That is, since the respective chip regions in the same group are spatially close to each other on the wafer, the difference in the manufacturing process conditions is smaller than the difference between the chip regions in the other groups, and the above-described semiconductor chip failure and It is useful for investigating and analyzing the relationship between the characteristic variation and the chip position on the wafer.

According to the second aspect of the present invention, the semiconductor chip is further provided with information effective for specifying the original wafer itself. Here, the information effective for specifying a wafer (hereinafter also referred to as wafer specifying information) means information useful for specifying an original wafer in which a chip area before being divided into semiconductor chips was present.

[0009] It is known that the manufacturing process conditions of each wafer vary slightly even for each wafer flowing in the same process line. Therefore, if information useful for specifying a wafer is provided for each chip area, it is possible to specify the original wafer even if a failure occurs or the characteristics of the semiconductor chips after the wafer division are varied. This makes it easier to investigate and analyze the relationship between semiconductor product defects and characteristic variations after mounting and the manufacturing process conditions given to the wafer, and to improve the manufacturing process to improve the yield of semiconductor chips. Becomes easier.

Since the actual history of each part of the manufacturing process is recorded and held, if the wafer to which the semiconductor chip belongs is specified, the manufacturing process history given to the wafer becomes clear. As the wafer identification information, different wafer numbers and wafer codes assigned to each wafer are preferable, but in order to reduce the number of numbers and codes, for example, they are spatially or temporally close in a manufacturing process. It is also possible to assign the same number or code to a plurality of wafers. For example, if the same wafer number is given to a group of wafers to be simultaneously subjected to heat treatment, the influence of the variation in the heat treatment conditions due to the wafer position in the furnace cannot be specified, but the variation in the characteristics of the semiconductor chip due to the variation in the manufacturing process conditions for each heat treatment. Defects can be grasped and analyzed. That is, since the wafers in the same group are close in time or space during the manufacturing process, the difference in the manufacturing process conditions is smaller than the difference between the wafers in the other groups, so that the above-described semiconductor chip It is useful for investigating and analyzing the relationship between defects and variations in characteristics and manufacturing process conditions given to wafers. Further, a code indicating a time immediately after the completion of the manufacturing process or the like can be given to each chip area as the wafer specifying information.

According to a third aspect of the present invention, in the configuration of the first aspect, the wafer itself to which the semiconductor chip once belongs belongs to a writable storage element formed separately from the semiconductor chip. Valid information is written,
Further, the writable storage element and the semiconductor chip are housed in the same package. With this configuration, the same operation and effect as the configuration according to claim 2 can be obtained.

According to a fifth aspect of the present invention, in the configuration of the fourth aspect, different chip position designation information is provided to all chip areas on the wafer. In this way, a complete determination of the chip area becomes possible, so that a detailed investigation of the manufacturing process history given to the semiconductor chip,
Analysis becomes possible. According to the configuration of claim 6, in the configuration of claim 4, the chip position designation information is formed in the chip area in a patterning step as a visually recognizable pattern.

According to the configuration of claim 7, in the configuration of any of claims 4 to 6, information effective for specifying a wafer is further added. According to the configuration of claim 8, in the configuration of any of claims 4 to 7, further,
The information providing step for providing the chip position specifying information and the wafer specifying information is performed in the same step as the step for forming a predetermined circuit function in the chip area. By doing so, the process extension can be avoided, and the number of new steps added can be reduced.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described with reference to the following examples. (Embodiment 1) An embodiment of a method of manufacturing a semiconductor device according to the present invention will be described below. In the schematic diagram shown in FIG. 1, a fixed number of chip regions 2 are defined and formed in a predetermined arrangement pattern on a wafer 1, and each chip region 2 has a different character string such as an alphabetic character string (here, one character). (Illustrated only in FIG. 3) are formed. Here, each wafer 1
After the same chip position designation code is given to the chip regions 2 at the same spatial position in FIG. 2, each chip region 2 is divided by dicing to become a semiconductor chip 3 respectively.

Thus, it is possible to know from which chip area on the wafer 1 the semiconductor chip divided from the wafer 1 has been cut. The steps of forming the chip position designation codes a to z in this embodiment will be described with reference to the process flow diagram of FIG. This process flow shows an acceleration sensor manufacturing step. First, in a surface resistance forming step 100, a silicon oxide film is formed on the surface of a silicon substrate, and a diffusion resistance is formed by ion implantation or deposition.

Next, as a contact hole forming step 200, a contact hole is formed by selectively opening a silicon oxide film on a predetermined portion of each chip region by ft lithography. At the same time, shapes (chip position designation codes) having different character strings or numbers are formed on a predetermined area of each chip (code pattern forming step, information adding step 200). In order to form a different shape on each chip in the wafer surface, the pattern formed on the mask is a pattern of a wafer size, and the same-size exposure is performed. Although reduction exposure is possible, a plurality of masks are naturally required to provide different shapes to all chip regions in the wafer surface.

Although the chip position designation code is formed by patterning a silicon oxide film here, it can be formed by patterning other materials (for example, a silicon substrate, an aluminum film, and a protective film). Next, in an aluminum wiring step 300, wiring is performed by aluminum film deposition and photolithography, a protection film (for example, a silicon nitride film) is formed in a protection film forming step 400, and a necessary portion (for example, a wire bonding pad) is formed by photolithography. Are selectively opened (opening step 400).

Next, as a wafer numbering step 500, in a non-chip region of the wafer, for example, a wafer number or a lot number is mechanically described on an exposed aluminum film.
Next, as an inspection step 600, the electrical characteristics of each chip area are inspected. The data at this time is stored in a computer together with a wafer number, a chip number, and the like.

Next, as a back surface processing / through groove forming step 700, a mass portion and a beam portion necessary for the acceleration sensor are formed by etching the back surface of the silicon substrate and forming a through groove. Thereafter, the electrical inspection of each chip as described above is performed again, and the data is similarly stored. Next, as a cutting step 800, each chip region 2 is diced from the wafer 1 to form a semiconductor chip 3. Each semiconductor chip 3 is layered for each wafer or lot and sent to the next assembling step 900,
It is assembled in a package 6 as shown in FIG. Here, in addition to the acceleration sensor semiconductor chip, a bipolar IC chip 4 for signal processing and an EPRO for electric trimming
The MOS IC chip 5 with M is mounted.

Next, as a trimming step 1000, the semiconductor product characteristics after mounting are adjusted by electric trimming.
At this time, information for identifying the wafer number and the lot number is written in the EPROM. The wafer number or lot number itself may be written, or the number of each semiconductor product after mounting may be written, and this number and the corresponding wafer number or lot number may be separately stored in the computer as an assembly history. Good. Further, a writable memory of another type may be used in place of the EPROM, or a thin film resistor fuse may be used. Also, if laser trimming of a metal thin film resistor is used, an area for writing an identification code is formed in advance, and the laser is trimmed during laser trimming.
The identification code may be formed by patterning the metal thin film with a laser beam. Alternatively, the same numbers and symbols as described above may be marked on a package or the like, for example, by printing.

Next, as an inspection step 1100, a characteristic inspection of each semiconductor product after chip mounting is performed, and a non-defective product is sent to a next step for assembling into an assembly. The data at this time is also stored in a computer or the like. In this embodiment, wafer identification is performed after assembly. However, if a writable memory of EPROM or a metal thin film is added on the semiconductor chip 3 and wafer identification information is written before dicing, the semiconductor chip after dicing can be identified. The trouble of layer-by-layer management for each wafer can also be reduced. In this case, the chip position identification information may be simultaneously written.

[Brief description of the drawings]

FIG. 1 is a schematic plan view showing an example of a semiconductor chip with a chip position designation code of the present invention.

FIG. 2 is a process diagram showing one embodiment of a manufacturing process of an acceleration sensor embodying the present invention.

FIG. 3 is a plan view showing a state where a semiconductor chip of the present invention is mounted.

[Explanation of symbols]

1 is a wafer, 2 is a chip area, and 3 is a semiconductor chip. a to z are chip position designation codes.

Claims (8)

[Claims] 1. A semiconductor device having a semiconductor chip cut and separated from a predetermined wafer, wherein the semiconductor chip has information effective for specifying a chip position on the wafer. 2. The semiconductor device according to claim 1, wherein said semiconductor chip has information effective for specifying said wafer itself. 3. The semiconductor device according to claim 1, wherein the storage element is formed separately from the semiconductor chip and has information effective for specifying the wafer itself, and the storage element and the semiconductor chip. And a package accommodating the semiconductor device. 4. A method of manufacturing a semiconductor device having semiconductor chips formed by forming a plurality of chip regions having a predetermined circuit function on a predetermined wafer and then dividing each of the chip regions. A method of manufacturing a semiconductor device, comprising: an information providing step of providing information effective for specifying its own chip position for each of the chip regions before the division. 5. The semiconductor device manufacturing method according to claim 4, wherein said information providing step includes a step of providing different chip position designation information to all chip regions on said wafer. Manufacturing method. 6. The method of manufacturing a semiconductor device according to claim 4, wherein said information providing step comprises a patterning step of forming a pattern for visually displaying said information in said chip region. Manufacturing method of a semiconductor device. 7. The method for manufacturing a semiconductor device according to claim 4, further comprising an information providing step of providing information effective for specifying said wafer itself to each of said chip regions before said division. A method for manufacturing a semiconductor device, comprising: 8. The method for manufacturing a semiconductor device according to claim 4, wherein the information providing step is performed in the same step as the step for forming the circuit function in the chip region. A method for manufacturing a semiconductor device, comprising: