JPH1140682A - Non-volatile semiconductor memory and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the data writing speed and voltage while maintaining and improving the charge holding characteristic. SOLUTION: A gate insulating film 6 interposed between a channel forming region 1a and a gate electrode 8 is formed by laminating a tunnel film 10, an intermediate film 12, and a top film 14 in this order from the bottom. The top film 14 is formed by laminating a plurality of insulating films (e.g. 14a and 14b), and the lowermost film 14a thereof is an oxide film. The intermediate film 12 is a silicon nitride film, etc., and the film thickness thereof is not larger than 5 nm. The tunnel film 10 may have a construction comprising an oxidized nitride film besides an oxide film. A transition layer with intermediate composition is interposed between the intermediate film 12 and the top film 14. Alternatively, there is a high concentration deep charge trap having a trap level greater than 2.0 eV near the interface between both of them.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a gate insulating film comprising a tunnel film, an intermediate film and a top film between a semiconductor channel formation region and a gate electrode. The present invention relates to a nonvolatile semiconductor memory device having a basic operation of electrically accumulating or extracting electric charges from a discrete carrier trap and a method of manufacturing the same. More specifically, the present invention relates to a top film structure capable of reducing the thickness of an intermediate film in order to improve characteristics by reducing the thickness of the intermediate film, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In a highly information-oriented society or a high-area network society, there is a great need for a large-capacity file memory. At present, a disk memory system using a disk such as a hard disk and an optical disk as a recording medium is used as a large-capacity memory system for storing data of 1 gigabyte (Gb) or more. Research to replace this large market with non-volatile semiconductor memories has recently been active. However, although the nonvolatile semiconductor memory meets the trend of miniaturization and weight reduction of hardware devices, at present the storage capacity is still insufficient, and
A batch erase type semiconductor memory (flash memory) having a large capacity of Gb or more has not been realized.

In order to increase the degree of integration of the nonvolatile semiconductor memory, the area occupied by the memory cell array and the peripheral circuit can be roughly classified by making full use of semiconductor fine processing technology or devising the circuit system and device structure of the memory cell. Currently, a method of reducing the size of the memory itself and a method of multiplying the value of the memory transistor constituting each memory cell and storing a plurality of bits in a single transistor to substantially increase the storage capacity with the same degree of integration are currently being energetic. Is being considered.

In the former method, miniaturization is performed according to a so-called scaling rule. However, in order to realize a large-capacity memory of 1 Gb or more by an FG (Floating Gate) type flash memory, there are various essential problems relating to scaling. In particular, it has been pointed out that it is difficult to lower the data writing voltage (see Nikkei Micro Devices January and February, 1997). That is, in the FG type flash memory, since the retention of charge at the floating gate depends only on the thickness of the tunnel oxide film, the theoretical analysis of the back tunneling current from the floating gate indicates that the thickness of the tunnel oxide film is small. Is 6n
It is physically limited to about m. However, before reaching this physical limit, the current FG type uses a high electric field of 10 MV / cm for writing data, so that
It is pointed out that there is a film thickness limit due to the stress leak of the tunnel oxide film. It is difficult to reduce the thickness of the tunnel oxide film to the theoretical value of 6 nm due to the limitation of the film thickness due to an increase in the stress leak current, and the practical limit of the tunnel oxide film is 8 nm.
For low-voltage writing, the tunnel oxide film must be thinned.However, the above-mentioned limit of thinning the tunnel oxide film is inconsistent with the scaling rule of low voltage, and scaling of the writing voltage becomes difficult. I have.

On the other hand, MONOS (Metal-Oxide-Nitride-O
xide Semiconductor) type non-volatile memory, the carrier retention in the SiN film, which is mainly responsible for the charge retention, is discrete and spreads in the film thickness direction and the plane direction, so that the data retention characteristic is the tunnel oxide film thickness. Besides, S
It depends on the energy and spatial distribution of the charge trapped by the carrier trap in the iN film. Therefore, the problem of thinning the tunnel oxide film is not as serious as that of the FG type.

FIG. 8 shows a basic structure of a conventional MONOS type nonvolatile memory transistor. In the MONOS nonvolatile memory transistor 100, a gate insulating film 110 including a tunnel oxide film 104, a SiN film 106, and a top oxide film 108 is formed on a channel formation region 102a of a silicon substrate 102.
, The gate electrode 112 is laminated. In FIG. 8, reference numeral 114 denotes a source impurity region and a drain impurity region formed in the silicon substrate with the channel formation region 102a interposed therebetween.

[0007]

However, the conventional MON
In the OS type non-volatile memory, there is a trade-off relationship between the data retention characteristic and the data writing speed and voltage, and while maintaining or improving the data retention characteristic at a satisfactory level, the speed of data writing and the reduction of the voltage are reduced. It was difficult to achieve. In order to satisfy the data retention characteristics at a high level, it is necessary to further optimize the thicknesses of the tunnel oxide film and the SiN film. However, for manufacturing reasons, SiN
At present, the problem is that simply optimizing the thicknesses of the tunnel oxide film and the SiN film cannot meet the trend of increasing the speed of data writing and lowering the voltage, because it is difficult to make the film thinner. .

[0008] The problems of the conventional MONOS type non-volatile memory are as follows: the relationship between the tunnel oxide film thickness and the SiN film thickness;
It is organized and described from two viewpoints.

Relationship between Tunnel Oxide Film Thickness and SiN Film Thickness As described above, the conventional MONOS type nonvolatile memory transistor has a problem that its data retention characteristics are inferior to the FG type nonvolatile memory transistor. Has achieved a data retention characteristic of 10 years at 85 ° C. by designing the tunnel oxide film or SiN film to be relatively thick.
However, in order to increase the writing speed and lower the voltage while maintaining the data retention characteristics, the tunnel oxide film and the Si
It has become necessary to optimize the thickness of the N film. There are two ways to optimize the film thickness. According to the first concept, the thickness of the tunnel oxide film is reduced to about 2.0 nm, and the thickness of the SiN film is relatively increased (to 10 nm or more). On the other hand, the second concept is to set the tunnel oxide film to about 2.
The SiN film is thinned to some extent by increasing the thickness to 5 nm to 3.0 nm (however, the SiN film thickness is about 5
nm is the limit).

In any of the optimization methods, data retention at 85 ° C. for 10 years is achieved, but the data write voltage (program voltage) is about 12 V in the former and about 10 V in the latter.
Is the limit. A single transistor in a memory cell
In the transistor cell, further reduction in the program voltage is difficult. In order to achieve even lower voltage at present, it is necessary to further reduce the thickness of the tunnel oxide film, and the data retention characteristics that deteriorate with this are added from the aspect of reducing stress leakage by adding a select transistor to each cell. Need to compensate. However, in this case,
As the cell area increases, a result that goes against the trend of higher integration and higher capacity is caused. As for the data writing speed (program speed), either the tunnel oxide film or the SiN film is relatively thick as described above, and at present, the speed is still not sufficiently increased to about 1 ms to 10 ms. If it is desired to achieve a higher programming speed, the programming voltage must be increased to 10 V or more. This is required to reduce the programming voltage, that is, to secure device reliability as device miniaturization progresses. It does not meet the requirement to reduce the circuit load for generating voltage.

In a MONOS type nonvolatile memory having a thickness limit of SiN due to manufacturing reasons , in order to prevent a decrease in the number of rewritable times of a memory transistor, holes can be effectively injected from a gate electrode into a SiN film by a top oxide film. Must be deterred. For this reason, the thickness of the top oxide film is at least about 3.5 nm to 4.5 nm,
It is empirically known that 4 nm or more is required. This top oxide film is usually formed by thermally oxidizing the SiN film. In this case, in the thermal oxidation process of the SiN film, if the underlying SiN film is thin, pinholes or uneven film quality may occur. The resulting abnormal oxidation may occur, and there is a certain limit in reducing the thickness of the SiN film in order to suppress this.

In the graph of FIG. 9, when a 4 nm top oxide film is formed, the limit of the remaining film thickness (final film thickness) after thermal oxidation of the SiN film was examined by observing an increase in film thickness due to abnormal oxidation. The results are shown. The horizontal axis in FIG. 9 indicates the final thickness of the SiN film, and the vertical axis indicates the insulating film (ONO film) formed on the substrate.
Shows the total film thickness. FIG. 9 also shows the results when the tunnel oxide film is subjected to high-temperature and short-time thermal nitridation (RTN) and when the RTN is not performed. When the final thickness of SiN is relatively large, the total thickness of the insulating film is about 10 nm to 15 nm. When the SiN film is thinned, in the case without RTN,
The total thickness of the insulating film sharply increases from around 8 nm.
This is because the oxidation progresses partially due to the pinholes of the SiN film and the unevenness of the film quality, and the top oxide film is partially connected to the tunnel oxide film. Thereafter, a large amount of Si is supplied from the substrate to increase the speed. It indicates that oxidation has occurred. The thickness limit of the SiN film required to form this top oxide film of 4 nm is improved by performing RTN, but is still about 5 nm. This indicates that it is difficult with the current process to reduce the remaining SiN film thickness to about 5 nm or less as a result of forming a top oxide film of 4 nm or more on the SiN film by thermal oxidation.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a nonvolatile semiconductor memory device having a basic operation of electrically storing or extracting electric charges in discrete carrier traps. By alleviating the restrictive condition that hinders the optimization of the gate insulating film structure, at least one of improvement of data retention characteristics, speeding up and lowering of voltage of data writing, and cell area reduction (cost reduction) is achieved. An object of the present invention is to propose a method of manufacturing a nonvolatile semiconductor memory device that can be achieved without sacrificing others, and to provide a nonvolatile semiconductor memory device having a new structure using the same.

[0014]

Means for Solving the Problems Charge retention of a MONOS type memory is achieved by bulk trapping of a relatively shallow SiN film,
Conventionally, two types of carrier traps, a deep trap existing near the interface between the SiN film and the top oxide film, have been described. In recent years, charge retention of a MONOS type memory mainly uses a relatively shallow bulk carrier trap (trap energy level: about 0.8 eV) of a SiN film under program voltage conditions for achieving high-speed writing on the order of ms. It was revealed. The inventor has
It was considered that the above-mentioned limit of the film thickness optimization can be overcome by mainly using a deep carrier trap existing near the interface with the top oxide film instead of the bulk carrier trap of the SiN film for charge retention. Also, it was considered that the active use of the deep carrier trap was effective in improving the data retention characteristics, and the effect of this improvement could be confirmed by a simulation described later. Then, it was found that it is important to reduce the thickness of the SiN film itself in order to mainly use a deep carrier trap. Based on this knowledge, the method of forming the top oxide film by thermal oxidation was reviewed to make the SiN film thinner. As a result, the thermal oxide film is kept to a necessary minimum, and the top oxide film for preventing the hole injection is secured by increasing the deposited film by the low pressure CVD method. It was concluded that high speed and low voltage could be achieved at the same time.

The present invention has been devised in view of the above circumstances, so to speak, MOONOS (Metal-Oxide-Oxide-Nitri
A non-volatile semiconductor memory having a gate insulating film structure of a (de-Oxide Semiconductor) type and a method for manufacturing the same are newly proposed. That is, in the nonvolatile semiconductor memory device according to the present invention, the gate insulating film interposed between the semiconductor channel forming region and the gate electrode of the memory transistor and including the charge storage means discretely formed in a plane is formed by the channel insulating film. What is claimed is: 1. A non-volatile semiconductor memory device comprising a tunnel film, an intermediate film, and a top film laminated in this order from a formation region side, wherein the top film is formed by laminating a plurality of insulating films, and a lowermost layer of the plurality of insulating films is formed. The film is an oxide film.

[0016] Preferably, the top film includes a first oxide film on the intermediate film and a second oxide film on the first oxide film. This is because a charge trap is not formed in the top oxide film. Further, from the viewpoint of preventing hole injection, the preferable thickness of the top film is 3.5 nm or more.

Preferably, the intermediate film is any one of a nitride film, a silicon nitride film, and an oxynitride film, and has a thickness of 5n.
m or less. Further, a transition layer having a composition intermediate between the intermediate film and the top film is interposed between the intermediate film and the top film, or the level of the trap energy (the energy difference from the conduction band) is 2. High concentration of deep charge traps greater than 0 eV. On the other hand, the tunnel film may include an oxide film on the channel formation region and an oxynitride film on the oxide film.

In the nonvolatile semiconductor memory device having such a configuration, the top film is composed of a plurality of films, and the lowermost film is an oxide film. The entire film thickness is changed to an intermediate film (for example, SiN
(Film or SiON film).
For this reason, the thermal oxidation time can be short, and even if the initial film thickness of the intermediate film is set to be small, abnormal oxidation (increased oxidation) during the formation of the top film, which has conventionally been a problem, is unlikely to occur. As a result, the thickness of the intermediate film can be reduced (for example, 5 nm or less).

In a conventional non-volatile semiconductor memory device, carrier traps in a gate insulating film for retaining charges are mainly bulk traps, which are discretely spread in the thickness direction and the plane direction of an intermediate film. Was. By making the intermediate film thinner, deep carrier traps formed near the interface with the top film are more actively used, so that the center of charge distribution (charge center) is defined by the intermediate film thickness. In comparison, the distance from the substrate is relatively large as compared with the related art. When the intermediate film is made thinner, the amount of charge retained by the bulk trap decreases, but the total carrier retention does not decrease because the deep carrier trap plays a main role in retaining the charge. Although the thinning of the intermediate film is disadvantageous in terms of charge retention, the charge in a deep carrier trap is hard to escape, and the charge center in the intermediate film is separated from the substrate, so that the charge retention characteristics do not deteriorate. Further, by reducing the thickness of the intermediate film, the thickness of the entire gate insulating film is reduced, which is advantageous for lowering the voltage of data writing. This means that if the write voltage does not need to be reduced, there is room for increasing the thickness of the tunnel film by reducing the thickness of the intermediate film. When the tunnel film is thickened, not only the charge retention characteristics are improved, but also a memory characteristic in which the gate threshold voltage is unlikely to be in a depletion region at the time of erasure and is saturated by enhancement is easily obtained.

On the other hand, as the thermal oxidation time is shortened, the time during which the device is exposed to a high temperature is shortened. As a result, suppression of impurity rearrangement, that is, fluctuations in the concentration distribution of the channel formation region in the substrate or the well, and the depth and concentration distribution of the source / drain regions are reduced. If this variation is too large, it is difficult to predict the final impurity distribution. However, in the present production method, since the above variation can be suppressed to a small value, the controllability of the impurity distribution is improved. As a result,
In order to obtain a desired gate threshold voltage or to suppress a short channel effect, an optimum impurity distribution is easily obtained.

In the method for manufacturing a nonvolatile semiconductor memory device according to the present invention, a tunnel film, an intermediate film, and a top film are sequentially formed on a channel formation region of a semiconductor prior to formation of a conductive film serving as a gate electrode of a memory transistor. A method for manufacturing a non-volatile semiconductor memory device, comprising forming a gate insulating film including charge storage means discretized in a plane by stacking, wherein said intermediate film is a film thicker than its final film thickness. Forming a thermal oxide film by thermally oxidizing the surface of the intermediate film when laminating the top film on the intermediate film, and then forming a CVD method on the thermal oxide film. And depositing an oxide film.

In this manufacturing method, after the surface of the intermediate film is thermally oxidized, an oxide film is deposited on the thermal oxide film by the CVD method. Therefore, in the thermal oxidation, a deep carrier trap near the interface with the intermediate film is high. The minimum required to be able to form the concentration is sufficient. C
In the case of VD, the film forming raw material is supplied not from the intermediate film but from the introduced gas, and no accelerated oxidation occurs even if the film is formed thick. Further, the CVD method has a lower deposition temperature than the thermal oxidation method, and the higher the proportion of the oxide film formed by the CVD method, the more the impurity rearrangement can be suppressed.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a nonvolatile semiconductor memory device and a method of manufacturing the same according to the present invention will be described in detail with reference to the drawings. The present invention proposes a gate insulating film structure of a memory transistor in which a deeper carrier trap can be mainly used than before. For this reason, the description here will focus on the configuration of the memory transistor and the method of manufacturing the memory transistor, focusing on the gate insulating film structure.

FIG. 1 shows a MONO according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating an element structure of an S-type memory transistor. 2 and 3 are cross-sectional views showing a modification of the gate insulating film structure of the MONOS memory transistor. In the figure, reference numeral 1 denotes a semiconductor substrate or well such as a silicon wafer having n-type or p-type conductivity, 1a denotes a channel formation region, and 2 and 4 denote a source region and a drain region of the memory transistor. The “channel forming region” in the present invention refers to a region in which a channel through which electrons or holes are conducted is formed inside the surface side, and as shown in FIG. 1, in addition to the surface region of the semiconductor substrate itself, There are various forms such as a surface portion of a well formed on the surface side of the semiconductor substrate, a surface portion of an epitaxial growth layer formed on a semiconductor substrate surface, or a semiconductor layer having an SOI (Silicon On Insulator) type insulating structure. The source region 2 and the drain region 4 are regions having high conductivity formed by introducing impurities of the opposite conductivity type to the channel formation region 1a into the semiconductor substrate 1 at a high concentration, and have various forms. Usually, a low-concentration impurity region called an LDD (Lightly Doped Drain) is often provided at the substrate surface position facing the channel forming region 1a of the source region 2 and the drain region 4.

On the channel forming region 1a, a gate electrode 8 of the memory transistor is stacked via a gate insulating film 6. The gate electrode 8 is generally made of polysilicon (doped poly-Si) doped with p-type or n-type impurities at a high concentration and made conductive, or a laminated film of doped poly-Si and refractory metal silicide. .

In the present embodiment, the gate insulating film 6 includes a tunnel film 10, an intermediate film 12, and a top film 1 in order from the lower layer.
4 (a first oxide film 14a and a second oxide film 14b).

In the present invention, the intermediate film 12 needs to form deep carrier traps at a high density between the intermediate film 12 and the thermal oxide film. For this reason, the intermediate film 12 is made of, for example, silicon nitride (SiN) or silicon oxynitride (SiON). You. This intermediate film 12 is thinner than before, that is, 5 nm or less.
The reason will be described later. The top film in the present invention may be a laminated film in which the lowermost film is a thermal oxide film,
There is no limitation on the number and type of upper layers on the thermal oxide film.
However, the film on the thermal oxide film is required not to be reduced in the thickness of the intermediate film at the time of film formation because of the thinning of the intermediate film 12. It is also necessary that the temperature at the time of film formation is lower than that of thermal oxidation, and that a trap not too deep between the film and the thermal oxide film be formed. As the simplest configuration of the top film that satisfies the above requirements, in the present embodiment, the top film is constituted by a thermal oxide film (first oxide film 14a) and a second oxide film 14b thereon. 2 oxide film 14b by CVD
It is a deposited film by the method. The thickness of the top film 14 should be at least 3.5 nm, preferably at least 4.0 nm, in order to effectively prevent the injection of holes from the gate electrode 8 and prevent the number of times data can be rewritten. is necessary.

In general, a deep carrier trap generated by thermal oxidation of a SiN film and formed near the interface between the two has a trap energy level (trap level: energy difference from the conduction band) of 2. 0
It is estimated to be about eV to 2.5 eV. Also,
The origin of the carrier trap of amorphous SiN is assumed to be a Si dangling bond, and has been confirmed by an electron spin resonance method (ESR method). The trap level of this Si dangling bond is measured by a spectroscopic method and is known to be about 2.5 eV.

This deep carrier trap is said to be formed if the thermal oxide film has a certain thickness, but the specific numerical value of the thickness is not known much. In this regard, of the 5 nm SiN film, when 1 nm is thermally oxidized, a 1.6 nm SiO ₂ film is formed. At this time, the shift amount of the gate threshold voltage Vth of the MONOS transistor due to charge injection becomes about 2 V. There is data.
From this, the thickness of the thermal oxide film (first oxide film 14a) may be smaller than the minimum thickness (3.5 nm) required as the top film to prevent injection of holes from the gate electrode 8. If at least about 1.6 nm, a practical V
It can be concluded that th soft amount is obtained.

As pointed out above, conventionally, all the film thickness required for the top film is formed by thermal oxidation.
When the N film is too thin, accelerated oxidation occurs (FIG. 9), and the film structure is destroyed, so that the SiN film has a thickness limit. For this reason, in the conventional MONOS type transistor, considering the in-plane uniformity of the film thickness and the process stability, the final S
It was difficult to reduce the thickness of the iN film to 5 nm or less. On the other hand, in the present invention, by forming the top film 14 into a plurality of layers (for example, a two-layer oxide film), the thickness of the lowermost thermal oxide film 14a is reduced and thermal oxidation is performed before accelerated oxidation occurs. After that, the film constituent material is supplied from the introduced gas, and the accumulation of the oxide film 14b by the CVD method without the concern of the accelerated oxidation is made possible. For this reason, the MONO according to the present invention
The S-type transistor has a structural feature that enables a gate insulating film structure to be stably formed without causing a reliability problem even when the thickness of the intermediate film 12 is small (for example, 5 nm or less). This is the reason why the film thickness can be reduced to 12.

It is generally considered that the tunnel film 10 is preferably formed of a SiO ₂ film formed by a thermal oxidation method in terms of characteristics. However, the tunnel film 10 may be formed of SiON. When the intermediate film 12 is made of SiN, if the underlying tunnel film 10 is made of SiON, although the characteristics are inferior, an increase in the roughness of the surface of the intermediate film 12 can be suppressed. There is an advantage that it is easy to optimize. Further, as a configuration having both advantages, as shown in FIG.
0 is a lower SiO ₂ film 10 a and an upper SiON film 10
b. There is no particular limitation on the film thickness of the tunnel film 10, but depending on the intended use or any of the characteristics described below, 2.0 nm to 3.
The film thickness can be appropriately set within a range up to 4 nm. An example of a more preferable (limited) film thickness range depends on whether or not the tunnel film 10 has been subjected to the RTN process. The case where the RTN is not performed is about 2.0 nm to 2.5 nm, and the case where the RTN is performed. Is about 2.6 nm to 3.2 nm.

In particular, when the intermediate film 10 is made of SiN, when it is thermally oxidized, the intermediate film 10 and the thermal oxide film 14a are positioned between the intermediate film 10 and the thermal oxide film 14a.
As shown in FIG. 3, a transition region whose composition gradually changes from SiN to SiO ₂ is formed. If this region is regarded as one layer (transition layer 13), FIG. Modification 2) and belongs to the category of the present invention. Although not particularly shown, a deep carrier trap in this case is expected to be formed in the transition layer 13 or in a region around the transition layer 13.

Next, a method for manufacturing the nonvolatile semiconductor memory device according to the present invention will be described. Since the main points of the present manufacturing method have been described in the above description, the manufacturing method and the characteristic portion of the entire transistor will be briefly supplemented here. The flow of the entire transistor manufacturing process is basically the same as the conventional one. That is, after forming an insulating isolation region, ion implantation for adjusting the gate threshold voltage Vth, and the like as necessary in the semiconductor substrate (or well) 1, the gate insulating film 6 is formed on the active region of the semiconductor substrate 1 via the gate insulating film 6. To form source / drain regions 2 and 4 in a self-aligned manner, forming an interlayer insulating film and forming contact holes, forming source / drain electrodes, and, if necessary, The non-volatile semiconductor memory device is completed through the formation of the upper layer wiring via the interlayer insulating layer, the overcoat film formation, the window opening step, and the like.

The present invention is characterized by the formation of the gate insulating film 6, particularly the step of forming the top films (the first and second oxide films 14a and 14b). First, a tunnel film 10 is formed on the active region (substrate surface defined by element isolation regions and the like) of the semiconductor substrate 1 with a required thickness, for example, 2.0 nm to 3.
It is set appropriately within the range up to 4 nm. The tunnel film 10 is formed by thermally oxidizing the substrate surface to form an SiO ₂ film (FIG. 1 or FIG. 3), and forming Si by thermally oxidizing the substrate surface.
The O ₂ film is nitrided to form an entire SiON film (FIG. 1 or FIG. 3), or a part of the thermally oxidized SiO ₂ film is nitrided to form an SiON film (FIG. 2). An optimal method is appropriately selected according to the material and the configuration. Next, an intermediate film 12 is formed on the tunnel film 10. The formation of the intermediate film 10 is performed by the CVD method. At this time, the introduced gas is appropriately selected according to the material (SiN or SiON) of the intermediate film 12. In setting the film thickness of the intermediate film 12, the final film thickness (5 nm or less) is taken into account in consideration of the film reduction due to the next thermal oxidation.
Is set to a value thicker than this. Then, a first oxide film 14a is formed by thermally oxidizing the surface of the intermediate film, and then CVD is performed on the first oxide film 14a.
The second oxide film 14b is deposited by a method, for example, a low pressure CVD method. The thickness of the first oxide film 14a is, for example, 1.6 n.
The thickness of the second oxide film 14b is preferably set to a predetermined value when the total thickness of the top film 14 is 3.5 nm or more. Thereafter, the process proceeds to the step of forming a conductive layer to be the gate electrode 8, and thereafter, the memory transistor is completed according to a conventional method.

Next, the advantage (effect) of forming the top film 14 from a plurality of films (in this example, the two-layer oxide films 14a and 14b) in the present invention is to improve the characteristics by reducing the thickness of the intermediate film 12. Stated by clarification.

Data Retention Characteristics In order to improve the data retention characteristics, it is important to increase the trap level and increase the distance between the center of gravity of the retained charges and the channel forming region 1a. Here, an analysis (simulation) was performed using a Landkist back tunneling model as an analysis model of the data retention characteristics, and the difference in the data retention characteristics depending on the trap level depth was examined from the analysis results. In this model, the relaxation constant (τ) of the dissipation of the electrode is described by a direct tunneling equation as shown below.

[0037]

(Equation 1) Here, τ _O is the intrinsic tunnel probability, P _OX is the tunnel probability of the oxide film, _PN is the tunnel probability of the nitride film, m ^* is the effective mass, φ ₂ is the conduction band discontinuity, φ _t is the trap level, W _OX
Indicates the thickness of the tunnel oxide film, and x indicates the distance from the interface between the tunnel oxide film and the nitride film.

FIGS. 4 to 6 are graphs showing data retention by simulation using a Landkist model as a physical model. Here, FIG.
FIG. 5 shows a case where a trap level of 1.5 eV is assumed, and FIG. 6 shows a case where a deep carrier trap whose trap level is 2.2 eV is assumed. In each of the figures, the charge amount is plotted as normalized by the initial charge. FIG. 7 is a graph showing a charge distribution as a setting condition. At this time, the film structure condition is that the tunnel oxide film thickness (without RTN processing) is 2.5 n.
m, the SiN film thickness was 4 nm, and the top oxide film thickness was 4 nm. Although the actual bulk traps are assumed to be distributed almost uniformly in the film thickness direction, the charge distribution is unevenly distributed on the top side similarly to the deep carrier traps in order to see the difference in the trap levels. Assuming the vicinity of the interface between the SiN film and the top oxide film, the carrier traps are distributed between approximately 3.4 nm and 4.0 nm in the SiN film starting from the other interface.

When the bulk trap shown in FIG. 4 has a voltage of 0.8 eV, the amount of retained charges decreases as the retention time elapses. In a relatively long time (after 2 hours), the amount of decrease is lo
It shows a tendency that is proportional to g (t). On the other hand, when the trap level of FIG. 5 is 1.5 eV, 0.8 e
It can be seen that the data retention characteristics are significantly improved as compared with the case of FIG. 4 using the V bulk trap. Also, it can be seen that when a deep carrier trap of 2.2 eV is used, the data retention characteristics are further improved. As a result, it was confirmed that when the deep carrier trap was mainly used, good data retention characteristics were exhibited even when the thickness of the SiN film was reduced to 4.0 nm. In addition, there is a report that the concentration of the deep carrier trap at the SiO ₂ / SiN interface is 1 to 2 × 10 ¹³ / cm ^2, and the numerical value indicates that the shift amount of the gate threshold voltage Vth of the memory transistor is 1. It is considered possible to set the voltage to about 5 V or more. Further, the above simulations can theoretically support that the Vth shift amount of 2.0 V was exhibited at the SiO ₂ /SiN=1.6 nm / ₄ nm in the actual device data described above.

The simulation using this Landkist model as a physical model is based on the case where the intermediate film 12 or the tunnel film 10 is made of SiON, and the case where the tunnel film 10 is made of the thermally oxidized silicon film 10a and the SiON film 10b (FIG. 2). Also went respectively. When the surface of the tunnel film 10 is SiON, although the physical constants such as the effective mass and the band mismatch value are different from those described above, basically similar results were obtained, and the intermediate film thickness was reduced to 4.0 nm. It was found that even in this case, good data retention characteristics were exhibited.

Operating Voltage in Data Writing / Erasing Another important performance index related to the gate insulating film structure is the operating voltage and writing / erasing time in data writing / erasing. In the data write operation in the MONOS type nonvolatile memory, the conduction mechanism of electrons in the insulating film is based on a modified FN (Fowler-Nordheim) Tunnel.
Because of the description of the ing mechanism, it is necessary to apply a sufficiently high electric field to the tunnel film and the SiN film even in low-voltage writing. For this purpose, it is important to reduce the thickness of the gate insulating film in terms of SiO ₂ film thickness. Conventionally, even if the surface of the tunnel film is subjected to RTN treatment, the SiN film
In consideration of the in-plane uniformity of the film thickness and the process stability, it was actually necessary to further increase the thickness (FIG. 9).
reference). In the present invention, the top film thickness is set to 4 nm as in FIG.
If formed, the thermal oxide film (first oxide film 14a) is 2n
m, the thickness of the intermediate film 12 can be reduced to about 4 nm. In this case, assuming that the electric field strength is the same as the conventional one, the calculation is such that the program voltage can be reduced from the conventional 10 V to 9 V or less. At this time, a program time of 1 ms or less can be expected. In addition, a program voltage of 8 V or less can be achieved by making the intermediate film 12 thinner than 4 nm, or further reducing the thickness of the top film 14 to 3.5 nm with the second oxide film 14b being 1.5 nm.

The thinning of the intermediate film 12 provides a margin for increasing the thickness of the tunnel film 10 without increasing the operating voltage. When the thickness of the tunnel film 10 is increased, further improvement in data retention characteristics, reduction in stress leak of the tunnel film 10 and improvement in the number of times of data rewriting can be expected, and it becomes easy to make the memory cell into one transistor. In a memory cell having a one-transistor configuration, it is necessary that the gate threshold voltage Vth of the memory transistor does not enter the depletion region and the memory cell always operates in the enhancement region. Further, even in the case of the depletion region, data can be read out while the source region 2 is positively biased, so that Vth after readout effectively becomes the enhancement region and becomes one.
A memory cell having a transistor configuration can be realized. Since it is easy to use one transistor, the selection transistor required for each cell in the conventional MONOS type nonvolatile semiconductor memory device can be omitted, the memory cell area can be reduced, and the cost due to the chip area can be reduced. Reduction can be achieved. As a result, a cell area equivalent to that of the NOR type, AND type, NAND type, DINOR type, etc. of the FG type nonvolatile semiconductor memory can be achieved even with the MONOS type nonvolatile semiconductor memory device. Furthermore, for applications where the reading speed is low, the areas of the memory transistor and the high breakdown voltage transistor can be reduced, and further cost reduction can be achieved.

In addition, since the program voltage used for data writing / erasing can be reduced, the process can be shared depending on the generation of the transistor. As a result, a part of a high-breakdown-voltage photomask is not required, and the cost is reduced. Can be achieved. As an example of this, for example, of a transistor forming photomask in a program circuit, a gate electrode is etched, a desired Vth adjustment ion implantation mask is formed (one for n-channel and one for p-channel), and an impurity region offset for increasing drain withstand voltage is used. In this case, a total of five photomasks (one for n-channel and one for p-channel) can be omitted.

In the thermal oxidation step of the intermediate film 12 in which a deep carrier trap of 2.0 eV or less is formed, the device is exposed to a high temperature of, for example, 900 ° C. to 1000 ° C. In the present invention, the thermally oxidized SiO ₂ film has a thickness of 1.6 nm to ₂ n.
Since the film thickness is only about m, which is less than half of the conventional thickness, the influence of high-temperature heating on the device is reduced. For example, impurity rearrangement can be suppressed. That is, the concentration distribution of the channel forming region 1a already formed on the semiconductor substrate 1,
Variations in the depth and concentration distribution of the source / drain regions 2 and 4 are reduced. If this variation is too large, it is difficult to predict the final impurity distribution. However, in the present production method, since the above variation can be suppressed to a small value, the controllability of the impurity distribution is improved. As a result, it becomes easier to obtain an optimum impurity distribution for obtaining a desired gate threshold voltage or suppressing a short channel effect.

[0045]

EXAMPLES Hereinafter, examples of the present invention will be described more specifically. In the following description, the structure of the gate insulating film and the method of forming the gate insulating film will be described, and the structure and the manufacturing method thereof that are not particularly described will be in accordance with the above-described embodiment.

Embodiment 1 This embodiment is a case where the tunnel film 10 is made of thermally oxidized silicon and the intermediate film 12 is made of SiN in the form shown in FIG.
The constituent thicknesses of the gate insulating film 6 are 2.5 nm for the tunnel oxide film 10, 4.0 nm for the intermediate film (SiN film) 12, 2.0 nm for the first oxide film (thermal oxide film) 14a, and 2.0 nm for the second oxide film. Oxide film (CVD deposited film) 14b is 2.0 nm. As the gate electrode 8, an n-type polysilicon electrode was used.

To form this gate insulating film, first, a silicon substrate is thermally oxidized by a high-temperature short-time oxidation method (RTO method) diluted with nitrogen to form a tunnel oxide film 10 (2.5 nm thick).
Was formed. Next, the SiN film 12 was deposited thicker by a low pressure CVD method so that the final film thickness became 4.0 nm. This CVD was performed at a substrate temperature of 650 ° C. using an introduction gas in which dichlorosilane (DCS) and ammonia were mixed. In forming a SiN film on this thermal oxide film,
In order to suppress the increase in the roughness of the finished film surface, the pretreatment (wafer pretreatment) of the base surface and the film formation conditions were optimized.
Unless wafer pretreatment is optimized, the surface morphology of the SiN film is poor and accurate film thickness measurement is not possible.
After sufficiently optimizing the wafer pretreatment, the film thickness was set in consideration of the decrease in the SiN film which would decrease in the next thermal oxidation step. The surface of the formed SiN film was oxidized by a thermal oxidation method to form a first oxide film 14a having a thickness of 2.0 nm. This thermal oxidation was performed at 950 ° C. in an H ₂ O atmosphere. As a result, a deep carrier trap having a trap level (energy difference from the conduction band of SiN) of about 2.0 eV to 2.5 eV is formed at a density of about 1 to 2 × 10 ¹³ / cm ² . In addition, the thermally oxidized silicon film was formed to 1.6 nm with respect to the SiN film 12 at 1 nm, and the SiN film thickness decreased at this ratio, and the final film thickness of the SiN film 12 became 4 nm. Subsequently, the second oxide film 1 is formed on the first oxide film 14a.
4b was formed to a thickness of 2.0 nm by a low pressure CVD method. This CVD was performed at a substrate temperature of 700 ° C. using an introduction gas in which DCS and N ₂ O were mixed. Finally, an n-type polysilicon film to be the gate electrode 8 was formed. Thereafter, gate electrode processing, source / drain regions and electrodes were formed according to a conventional method.

The characteristics of the thus-produced nonvolatile memory transistor were evaluated. As a result, it was confirmed that good characteristics as expected were obtained. That is,
Regarding the operation speed, the writing time was 0.2 ms (writing voltage 9 V), and the erasing time satisfied 50 ms for the block erasing. Since the carrier trap is spatially discretized, the number of times of data rewriting was satisfactory and satisfied 1 million times. In addition, the data retention time is the data rewrite 10
Even after 100,000 times, 85 years was satisfied for 10 years.

Embodiment 2 This embodiment is a case where the intermediate film 12 of the embodiment 1 is not a SiN film but an SiON film. Other films, that is, the tunnel film 10, the first oxide film 14a, and the second oxide film 14
The configuration (material and film thickness) of b and the film forming method are the same as those in the first embodiment. The steps after the formation of the gate electrode 8 are the same as those in the first embodiment.

In the formation of the intermediate film 12, S is formed by a low pressure CVD method.
An iON film was deposited thicker by a predetermined amount than the final film thickness of 4.0 nm, that is, by an amount reduced by thermal oxidation in the next step. This CV
D was performed at a substrate temperature of 650 ° C. using an introduction gas obtained by mixing N ₂ O in addition to DCS and ammonia. At this time, for the same reason as in Example 1, CVD was performed after optimizing the pretreatment and the film forming conditions for the surface of the thermal oxide film serving as the base of the SiON film. Under the same conditions as in Example 1, the surface of the SiON film was thermally oxidized to form a first oxide film 14a. This allows
A deep carrier trap is formed at the same trap level and density as in the first embodiment. Thereafter, the transistor was completed through the same steps as in Example 1.

The characteristics of the thus-produced nonvolatile memory transistor were evaluated. As a result, it was confirmed that good characteristics as expected were obtained. That is,
Regarding the operation speed, the writing time was 0.2 ms (writing voltage 9 V), and the erasing time satisfied 50 ms for the block erasing. Since the carrier trap is spatially discretized, the number of times of data rewriting was satisfactory and satisfied 1 million times. The data retention time was 10 years at 85 ° C.

Embodiment 3 In the present embodiment, the tunnel film 10 of the embodiment 1 is formed not by the thermal oxide film itself but by nitriding the thermal oxide film to form a SiON film. The thickness of the tunnel film 10 was 2.8 nm, which was slightly thicker than that of the first embodiment. Other films, ie, intermediate film 1
2. The configurations (materials and film thicknesses) of the first oxide film 14a and the second oxide film 14b and the film forming method are the same as those in the first embodiment. The steps after the formation of the gate electrode 8 are also the same as those in the first embodiment.
Is the same as

In forming the tunnel film 10, a silicon substrate is thermally oxidized by a high-temperature short-time oxidation (RTO) method in which oxygen is diluted with nitrogen, and a thermally oxidized silicon film (2.8 nm in thickness) is first formed.
Was formed. Next, the thermally oxidized silicon film was nitrided using a short-time nitridation (RTN) method, so that the entire silicon oxide film was turned into a SiON film. The oxynitridation of all the thermal oxide films was achieved by performing a heat treatment at 1000 ° C. for several minutes in a gas atmosphere such as NH ₃ or N ₂ O. After that, as in Example 1,
SiN film 1 by CVD with optimized pretreatment and film formation conditions
2 was formed. At this time, the film controllability was improved from that of Example 1. Thereafter, the transistor was completed through similar steps. Also in this case, a deep carrier trap is formed at the same trap level and density as in the first embodiment during the thermal oxidation for forming the first oxide film 14a.

The characteristics of the thus manufactured non-volatile memory transistor were evaluated. in this case,
Since the tunnel film was SiON, the writing speed was slightly lower than that in Example 1 in which this was a thermal oxide film, but it was confirmed that other characteristics were the same as in Example 1 and good characteristics were obtained. . That is, as for the operating speed, the writing time was 1 ms (writing voltage 9 V), and the erasing time was 50 ms for the block erasing. Since the carrier trap is spatially discretized, the number of times of data rewriting was satisfactory and satisfied 1 million times. The data retention time was 10 years at 85 ° C.

Embodiment 4 In this embodiment, the tunnel film 10 of the embodiment 1 is replaced with the thermal oxide film 1.
This is a case where a two-layer film structure of Oa and SiON film 10b is used. The thickness of the tunnel film 10 was 2.4 nm for the thermal oxide film 10a and 0.4 nm for the SiON film 10b. The configuration (material and film thickness) of the other films, that is, the intermediate film 12, the first oxide film 14a, and the second oxide film 14b, and the film forming method are as follows.
This is the same as the first embodiment. The steps after the formation of the gate electrode 8 are the same as those in the first embodiment.

In forming the tunnel film 10, a silicon substrate is thermally oxidized by a high-temperature short-time oxidation (RTO) method in which oxygen is diluted with nitrogen, and first, a thermally oxidized silicon film 10a (having a thickness of 2.8) is formed.
nm). Next, high temperature short time nitriding (RTN)
The SiON film 10b was formed from the surface layer (thickness: 0.4 nm) of the thermal silicon oxide film 10a by using the method. Thereafter, as in Example 1, the SiN film 12 was formed by CVD in which the pretreatment and the film formation conditions were optimized. At this time, the film controllability was improved from that of Example 1. Thereafter, the transistor was completed through similar steps. Also in this case, a deep carrier trap is formed at the same trap level and density as in the first embodiment during the thermal oxidation for forming the first oxide film 14a.

The characteristics of the thus manufactured non-volatile memory transistor were evaluated. in this case,
Example 1 since only the surface of the tunnel film was SiON
The same characteristics were obtained. That is, with respect to the operation speed, the writing time was 0.2 ms (writing voltage 9 V), and the erasing time was 50 ms in the block erasing. Since the carrier trap is spatially discretized, the number of times of data rewriting was satisfactory and satisfied 1 million times. The data retention time was 10 years at 85 ° C.

In the above-described first to fourth embodiments, the case where the gate electrode 8 is made of n-type polysilicon is shown. However, when the gate electrode 8 is made of p-type polysilicon, the erasing characteristics are particularly improved. Needless to say, the present invention is applicable.

[0059]

According to the MOONOS type nonvolatile semiconductor memory device newly proposed in the present invention, the carrier retention at the upper interface of the intermediate film, which is deeper than 2 eV, is used for the electric charge retention. Can be maintained or improved. Especially, Modified FN Tunne
The ling mechanism can improve the data retention characteristic, which is a drawback of the MONOS type nonvolatile semiconductor memory device, without deteriorating the characteristics on the write side.

Further, by reducing the thickness of the intermediate film, the data writing voltage,
At least one of the speeds can be reduced. By reducing the data write voltage, it is possible to secure device reliability and to reduce a circuit load for generating a high voltage as the miniaturization progresses.

The reduction in the thickness of the intermediate film leaves room for increasing the thickness of the tunnel film without deteriorating the voltage and speed during writing. Therefore, it is easy to realize an always-enhanced memory cell in which the gate threshold voltage Vth of the memory transistor does not enter the depletion region at the time of erasing and saturates in the enhancement region. As a result, it is easy to achieve a one-transistor memory cell. If the thickness of the tunnel film is increased and the gate threshold voltage Vth of the memory transistor hardly enters the depletion region, injection of holes is suppressed. Therefore, the deterioration of the tunnel film due to holes, which is conventionally known, is suppressed, and writing / erasing is prevented. The repetition characteristics are improved.

In a one-transistor memory cell, the selection transistor can be omitted, so that the memory cell area can be reduced, and the cost and the capacity can be reduced. From the viewpoint of reducing the data write voltage, cost reduction and large capacity can be achieved by reducing the area of the memory transistor and the high breakdown voltage transistor. In addition, this voltage reduction enables lower power consumption by reducing the voltage amplitude. Further, depending on the generation of the transistor, it is possible that the transistor in the program circuit used for writing / erasing and the transistor in the logic circuit used for reading have the same gate oxide film thickness depending on the generation of the transistor. If the gate oxide film thickness can be made the same, a part of the photomask of the high breakdown voltage circuit becomes unnecessary in addition to the common use of the process, which leads to further lower cost.

As described above, according to the present invention, the optimization limit of the gate insulating structure, which has been pointed out conventionally, is overcome by reducing the thickness of the intermediate film in the gate insulating structure of the MONOS transistor. As a result, there is a huge gap in realizing a large-capacity nonvolatile semiconductor memory with a fine gate length (0.18 μm generation or later).

[Brief description of the drawings]

FIG. 1 is a sectional view showing an element structure of a MONOS type memory transistor according to an embodiment of the present invention.

FIG. 2 is a sectional view showing a modification of the gate insulating film structure of the MONOS type memory transistor of FIG. 1;

FIG. 3 is a sectional view showing another modification of the gate insulating film structure of the MONOS type memory transistor of FIG. 1;

FIG. 4 shows a graph of data retention by simulation using a Landkist model as a physical model, in which a trap level of 0.8 eV is assumed.

FIG. 5 shows a graph of the data retention, in which the trap level is 1.5 eV.

FIG. 6 shows a graph of the data retention, and assumes a case where a deep carrier trap having a trap level of 2.2 eV is assumed.

FIG. 7 is a graph showing a charge distribution as a setting condition in the simulations of FIGS. 4 to 6;

FIG. 8 is a sectional view showing a basic structure of a conventional MONOS type nonvolatile memory transistor.

FIG. 9 is used to point out a conventional problem.
11 is a graph showing the result of examining the limit of the remaining film thickness (final film thickness) of a SiN film after thermal oxidation when forming a 4 nm top oxide film by observing an increase in film thickness due to abnormal oxidation.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 1a ... Channel formation region, 2 ... Source region, 4 ... Drain region, 6 ... Gate insulating film, 8 ... Gate electrode, 10 ... Tunnel film, 10a ... Thermal oxide film, 10b
... SiON film, 12 ... intermediate film, 14 ... top film, 14a
... first oxide film (thermal oxide film), 14b ... second oxide film.

Claims (19)

[Claims] A gate insulating film interposed between a channel forming region of a semiconductor and a gate electrode of a memory transistor and including charge storage means discretely formed in a plane; What is claimed is: 1. A non-volatile semiconductor storage device comprising an intermediate film and a top film, wherein the top film is formed by laminating a plurality of insulating films, and a lowermost film of the plurality of insulating films is an oxide film. Non-volatile semiconductor storage device. 2. The non-volatile semiconductor according to claim 1, wherein said top film comprises a first oxide film on said intermediate film and a second oxide film on said first oxide film. Storage device. 3. The nonvolatile semiconductor memory device according to claim 1, wherein said top film has a thickness of 3.5 nm or more. 4. The method according to claim 1, wherein the intermediate film is a nitride film, a silicon nitride film,
2. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is any one of an oxynitride film. 5. The nonvolatile semiconductor memory device according to claim 1, wherein said intermediate film has a thickness of 5 nm or less. 6. The nonvolatile semiconductor memory device according to claim 1, wherein a transition layer having an intermediate composition between said intermediate film and said oxide film is interposed between said intermediate film and said top film. 7. The nonvolatile semiconductor memory device according to claim 1, wherein a deep charge trap having a trap energy level of more than 2.0 eV is provided at a high concentration near an interface between said intermediate film and said top film. 8. The nonvolatile semiconductor memory device according to claim 1, wherein said tunnel film comprises an oxide film on said channel formation region and an oxynitride film on said oxide film. 9. The non-volatile semiconductor memory device according to claim 1, wherein the memory cell of the non-volatile semiconductor memory device has a single-transistor configuration in which the memory cell has a single transistor. 10. The nonvolatile semiconductor memory device according to claim 5, wherein a deep charge trap having a trap energy level higher than 2.0 eV is provided at a high concentration near an interface between said intermediate film and said top film. 11. Prior to forming a conductive film serving as a gate electrode of a memory transistor, a tunnel film, an intermediate film, and a top film are sequentially laminated on a channel forming region of a semiconductor, thereby being discretely planarized. What is claimed is: 1. A method for manufacturing a non-volatile semiconductor storage device, comprising: forming a gate insulating film including a charge storage means, wherein the intermediate film is formed on the tunnel film with a thickness greater than a final thickness thereof. In stacking the top film on the film, the surface of the intermediate film is thermally oxidized to form a thermal oxide film, and then the oxide film is deposited on the thermal oxide film by a CVD method. Production method. 12. The method of manufacturing a nonvolatile semiconductor memory device according to claim 11, wherein in the step of laminating the top film, a total thickness of films constituting the top film is set to 3.5 nm or more. 13. The method according to claim 11, wherein said intermediate film is one of a nitride film, a silicon nitride film, and an oxynitride film. 14. The film thickness of the intermediate film after being formed is set to a film thickness such that the final film thickness is 5 nm or less.
3. The method for manufacturing a nonvolatile semiconductor memory device according to 1. 15. The method for manufacturing a nonvolatile semiconductor memory device according to claim 11, wherein a transition layer having an intermediate composition is formed between said intermediate film and said thermal oxide film by said thermal oxidation. 16. The non-volatile memory according to claim 11, wherein a deep charge trap having a trap energy level larger than 2.0 eV is formed at a high concentration near an interface between said intermediate film and said thermal oxide film by said thermal oxidation. Of manufacturing a nonvolatile semiconductor memory device. 17. The method for manufacturing a nonvolatile semiconductor memory device according to claim 11, wherein in forming the tunnel film, after forming an oxide film on the channel formation region, the surface of the oxide film is thermally nitrided. 18. A memory cell of the nonvolatile semiconductor memory device, wherein the memory cell has a single transistor.
The method for manufacturing a nonvolatile semiconductor memory device according to claim 11, wherein the method has a transistor configuration. 19. The non-volatile memory according to claim 14, wherein a deep charge trap having a trap energy level larger than 2.0 eV is formed at a high concentration near an interface between the intermediate film and the thermal oxide film by the thermal oxidation. Of manufacturing a nonvolatile semiconductor memory device.