JPH11354741A - Dynamic RAM - Google Patents

Abstract

(57) [Problem] To provide a dynamic RAM provided with a redundant circuit realizing substantial rescue efficiency and high-speed operation. SOLUTION: In a dynamic RAM in which a plurality of sub-arrays are provided in the direction of complementary bit lines, the number of normal word lines provided in a sub-array in which redundant word lines are provided is provided in the direction of the complementary bit lines. The number is set to be smaller than the number of normal word lines in the subarray in which the word lines are not arranged.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology effective when used as a defect repair technology in a dynamic RAM (random access memory).

[0002]

2. Description of the Related Art A defect remedy method in which a defective word line is switched to a redundant word line is disclosed in JP-A-8-55494, JP-A-5-334896, and JP-A-2-192.
No. 100 publication. This rescue method employs an Any-to-Any method in which switching from a normal word line to a redundant word line is performed freely across memory mats (or subarrays).

[0003]

The switching from the normal word line to the redundant word line is performed as follows. First
Then, a memory access is made to the memory cell of the normal word line, and if the bit is defective, the address is recorded.
Second, the fuse in the address comparison circuit corresponding to the defective bit address is cut by irradiating a laser beam or flowing a current. The address of the defective bit is stored by setting the cutting and non-cutting of the plurality of fuses in the fuse set. In a single chip, a plurality of bit sets can be relieved by having a large number of fuse sets for each of a word system and a column system.

In the memory access after these procedures, the external address and the defective bit address in the fuse set are compared, and if they do not match, a normal memory cell on a normal word line or a normal column selection line is accessed. On the other hand, when they match, a redundant word line or a redundant column select line is selected to access the redundant memory cells connected to them. In such an address remedy method, the number of logic stages from the address input to the redundant word line or the redundant column select line slightly increases due to the logical operation of the comparison circuit, so that the access time to the redundant memory cell is normal. There was a tendency for the access time to the memory cell to be slower.

In the above-mentioned Any-to-any method, replacement from a normal word line to a redundant word line can be freely performed across memory mats (or subarrays), so that relief efficiency can be increased. However, memory cells connected to an overwhelmingly large number of normal word lines and memory cells connected to a relatively small number of redundant word lines are formed to have the same conditions (bit line capacity, sense amplifier constant). As a result, the yield due to the signal amount between the memory cell connected to the redundant word line and the memory cell of the normal word line becomes the same, and the defect due to the above signal amount also occurs in the redundant word line with the same probability as the normal word line. I noticed a problem that the rescue efficiency deteriorated because it occurred.

SUMMARY OF THE INVENTION An object of the present invention is to provide a dynamic RAM having a redundant circuit which realizes a substantial rescue efficiency and a high speed operation. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in a dynamic RAM in which a plurality of sub-arrays are provided in the direction of complementary bit lines, the number of normal word lines provided in the sub-array in which redundant word lines are provided is determined by the number of normal word lines provided in the direction of the complementary bit lines. Is set to be smaller than the number of normal word lines in the subarray in which the array is not arranged.

As a result, the bit line capacity of the sub-array including the redundant word lines can be reduced, and higher yield and higher speed can be realized by increasing the bit line signal voltage. Furthermore, by making the sub-array consisting of only normal word lines overwhelmingly larger than the number of sub-arrays containing redundant word lines,
The number of sub-array divisions, that is, the number of sense amplifier rows can be reduced, and both improvement in yield and reduction in chip area can be achieved.

[0009]

FIG. 1 is a schematic layout diagram showing one embodiment of a dynamic RAM to which the present invention is applied. In the figure, the main part of each circuit block constituting the dynamic RAM to which the present invention is applied is shown so that it can be understood. Are formed on one semiconductor substrate.

In this embodiment, although not particularly limited, the memory array is divided into four as a whole. The central part 1 is divided into right and left parts with respect to the longitudinal direction of the semiconductor chip.
4 is provided with an input / output interface circuit including an address input circuit, a data input / output circuit, and a bonding pad row, and a power supply circuit including a booster circuit and a step-down circuit. Column decoder regions 13 are arranged in portions of both sides of the central portion 14 in contact with the memory array.

As described above, in each of the four memory arrays divided into two on the left and right sides and two on the upper and lower sides with respect to the longitudinal direction of the semiconductor chip, the main row decoder is disposed at the upper and lower central parts in the longitudinal direction. An area 11 is provided. Main word driver regions 12 are formed above and below the main row decoder, and drive the main word lines of the vertically divided memory array.

The memory cell array (subarray) 15
Are formed so as to be surrounded by the sense amplifier region 16 and the sub-word driver region 17 with the memory cell array 15 interposed therebetween, as shown in the enlarged view. An intersection between the sense amplifier area and the sub-word driver area is an intersection area (cross area) 18. The sense amplifiers provided in the sense amplifier region 16 are configured by a shared sense method, and except for the sense amplifiers arranged at both ends of the memory cell array, complementary bit lines are provided on the left and right around the sense amplifier. Selectively connected to the complementary bit lines of the memory cell array.

In this embodiment, a memory cell array (hereinafter, referred to as a sub-array) is composed of a sub-array 151 including only normal word lines and a sub-array 152 provided with normal word lines and redundant word lines. . However, considering the bit lines provided to intersect with the word lines, they are classified into four types as described later.

The sub-array 151 includes, but is not limited to, 512 word lines (sub-word lines) and 256 pairs of complementary bit lines. The above sub-aire 152
Consists of 256 word lines (sub-word lines) and 32 redundant word lines, and 256 pairs of complementary bit lines are provided to intersect.

As described above, the memory arrays divided left and right with respect to the longitudinal direction of the semiconductor chip are arranged in pairs. In the two memory arrays thus arranged in pairs, the main row decoder region 11 and the main word driver 12 are arranged in the center. The main word driver 12 generates a selection signal of a main word line extended so as to penetrate the one memory array. The main word driver 12
Also, a driver for selecting a sub-word is provided, and extends in parallel with the main word line to form a selection signal for the sub-word selection line, as described later.

In one memory array divided into four, seven sub-arrays 151 are provided in the bit line direction, and two sub-arrays 152 are provided. Therefore, the number of subword lines provided in one memory array is 512 × 7 + 256 × 2 = 4096, and 16 subarrays are provided in the word line direction, so that about 4096 pairs of complementary bit lines are provided. Since four such memory arrays are provided for the entire memory chip 10, the storage capacity of the entire memory chip 10 is 4 × 4K ×
4K = 64M bits.

The one memory array is divided into 16 in the main word line direction. A sub-word driver (sub-word line driving circuit) 17 is provided for each of the divided sub-arrays 15. Sub word driver 17
Form a selection signal for a sub word line that is divided into 1/16 the length of the main word line and extends in parallel with the length. In this embodiment, in order to reduce the number of main word lines, in other words, to reduce the wiring pitch of the main word lines, there is no particular limitation. Is arranged with eight sub-word lines. As described above, in order to select one sub-word line from sub-word lines divided into eight in the main word line direction and eight each being assigned to the complementary bit line direction, a sub-word selection driver is used. Be placed. The sub-word selection driver is extended in the arrangement direction of the sub-word driver.
A selection signal for selecting one of the sub-word selection lines is formed.

FIG. 2 shows a memory mat configuration diagram of an embodiment of the dynamic RAM according to the present invention. This embodiment shows a configuration diagram of a memory mat in which one memory array is divided in the bit line direction among the memory chips in which the memory array is divided into four as described above. In the example of (A), one memory array is composed of nine sub-arrays of # 1 to # 9 arranged in the bit line direction, and in the example of (B), ten memory arrays of # 1 to # 10. It consists of sub-arrays.

The example (A) corresponds to the embodiment of FIG. 1, and each of the sub-arrays # 1 to # 3 and # 6 to # 9 consists of only normal word lines in the bit line direction. 51
Two sub-word lines are arranged. In contrast, # 4
And the two sub-aires # 5 each have 25
Six regular sub word lines and 32 redundant word lines RW are provided. In other words, the two sub-arrays # 4 and # 5 are divided into two sub-arrays each having 512 word lines, and each of the sub-arrays has 32 redundant word lines R.
It should be understood that W is added. That is, the decoder for selecting the sub-word line decodes the address signal having the binary weight and selects the sub-word line.
Twelve normal word lines are divided into two to form subarrays # 4 and # 5 having 256 normal word lines.

In the embodiment of (B), the ten subarrays are divided into two equal parts in the upper and lower parts, and # 1, # 3 and # 5 are divided into five in the upper half.
There are only 12 normal word lines, and # 2 and # 4 are 256 normal word lines and 16 redundant word lines RW each. In the lower half, # 6, # 8 and # 10 are 51
There are only two normal word lines, and # 7 and # 9 are 256 normal word lines and 16 redundant word lines RW each. The sub-array # 5, which is divided into two sets arranged in the bit line direction in this way and divided into two memory mats each having 2K, is provided with no redundant word line in # 6. It is.

In both cases (A) and (B), the redundant word line is provided in the sub-array having few normal word lines.
The amount of memory cell signal when a redundant word line is selected can be increased, and the yield of redundant memory cells can be higher than that of normal memory cells. In addition, if the bit line initial signal amount is large, the sense amplifier amplification time becomes faster, and as a result, the access time of the redundant memory cell can be made shorter. If the redundant word lines are not located at the ends of the sub-array but at the center as shown, the manufacturing conditions can be stabilized and higher yield can be achieved.

In the configuration (A), a defect of any of the normal word lines # 1 to # 9 is replaced with 64 redundant word lines in # 4 or # 5. In the configuration of (B),
Relief is independently performed for each of the 2K word line sets in the upper and lower portions. For example, the word line defects generated in # 1 to # 5 are repaired using the redundant word lines provided in # 2 and # 4, and the word line defects generated in # 6 to # 10 are corrected for # 7 and # 10.
9 is repaired by using the redundant word line. Dividing the repair unit into two sets has the following advantages.

The refresh cycle of a dynamic RAM having a storage capacity of 64 Mbits as described above is generally determined to be 4K (4096) cycles. Therefore, in normal operation, in the above four memory arrays,
At the same time, one main word line and its corresponding 16 sub-word lines (16 sub-arrays) are selected, and the 4K refresh operation is performed.

In order to perform a disturb refresh test in a short time as a test mode, when a 2K refresh operation is provided, the memory array is
K and the upper word line Wi and the lower Wi + 2
The word line of address 048 is selected at the same time. That is, the decoding operation of the address of the most significant bit of the X-system address signal is invalidated, and thereby the upper half and the lower half of the memory array are simultaneously selected. In the dynamic RAM of the above (B), the word line defect generated on the upper side is determined by the upper sub-array #.
Simple rule of switching to any redundant word line in # 2, # 4, and switching to any redundant word line in the lower sub-arrays # 7 and # 9 for any defective lower word line. , The 2K refresh operation can be performed under the Any-to-Any remedy method.

Since there is no redundant word line in central sub-arrays # 5 and # 6, sense amplifier SA provided between sub-array # 5 and sub-array # 6 can allocate redundant word lines as described above. The word line of sub-array # 5 or sub-array # 6 is not selected for repairing a defective word line. Therefore, in the decoding operation of the address signal in which the most significant bit is invalidated, the word lines of the sub-array # 5 and the sub-array # 6 are not simultaneously selected, and the independent half-to-any method and the shared sense Conflict of sense amplifiers can be avoided while employing the amplifier system.

FIG. 3 shows a memory array configuration of another embodiment of the dynamic RAM according to the present invention. In this embodiment, the memory array is divided into four, as in FIG. 1, but the direction of the word lines and bit lines provided in each is reversed from that of the embodiment of FIG.
As shown in (A), word lines of 16K bit lines are arranged in the longitudinal direction of the memory chip, and bit lines of 4K in the short side direction of the memory chip are arranged. That is, the word lines are not extended in the longitudinal direction of the chip as shown in FIG. 1, but are extended in the short side direction of the chip. The bit lines are correspondingly extended in the chip longitudinal direction.

Accordingly, in the peripheral circuit, the X decoder XDEC and the main word driver MWD are arranged near the center in the chip longitudinal direction, and the Y decoder YDEC is arranged near the center in the chip short direction. Bonding pads are arranged in the central portion in the longitudinal direction of the chip, and corresponding peripheral circuits such as an address buffer and a data input / output circuit are provided.

This embodiment also has a storage capacity of about 64 Mbits as described above. With such a configuration, the outer shape of the chip can be substantially the same as that of the 8KW × 8KBL memory chip shown in FIG. The reason is that the pitch of the word lines and the pitch of the bit line pairs have a relationship of about 1: 2. From the viewpoint of the memory bank B # 0, since there are only 2K bit line pairs, two word lines are selected to select 4K bit line pairs. Thus, the same read / write selection operation for one bank as in the memory array of FIG. 1 can be performed.

In the 4K refresh mode of FIG. 3B, eight word lines may be selected, two in each of the four memory banks B # 0 to B # 3. In the 2K refresh mode (one of the test modes) of FIG. 3C, in order to complete the refresh in 2K cycles, four memory banks B # 0 to B # 3 each have four memory banks B # 0 to B # 3, for a total of 16 memory banks. Select a word line. As described above, the following sub-array configuration is adopted in order to select two or four word lines simultaneously for each memory bank.

FIG. 4A shows a case where only the 4K refresh is supported, and the subarrays # 1 to # 9 and # 10 to
It is divided into two sets like # 18. Of the subarrays # 1 to # 9, # 1 to # 6 and # 9 have only 512 normal subword lines, while the remaining two # 7
And # 8 have 256 normal sub-word lines and 32 redundant word lines RW. Similarly, the above # 1
Of the subarrays 0 to # 18, # 10 and # 13 to # 1
8 has only 512 normal sub-word lines, and the remaining two # 11 and # 12 have 256 normal sub-word lines and 32 redundant word lines RW.

Also in this configuration, the sense amplifier uses two shared sub-arrays # 9 and # 1 provided at the boundary between the two sets of sub-array groups in order to use the shared sense system.
0 has no redundant word line. That is, the sub-array at the boundary is composed of only normal word lines.
This is because any one of the two sets of sub-arrays is simultaneously selected, and thus the Any-to-an
As described above in adopting y-type defect relief, #
9 and # 10 are indispensable to avoid competition of the sense amplifier.

FIG. 4B shows the sub-arrays # 1 to # 5, # 6 to # 5 so that the same chip can support both 4K refresh (normal refresh) and 2K refresh (one of the test modes). # 10, # 11 to # 15
And # 16 to # 20, which are divided into four sets of 2K each. Of the subarrays # 1 to # 5, # 1, # 2, and # 5 have only 512 normal subword lines, and the remaining two # 3 and # 4 have 256 normal subword lines. And 32 redundant word lines RW. Similarly, the other sets are also constituted by combinations of the above five subarrays, and the subarrays at the boundaries of each set are subarrays consisting only of normal word lines for the same reason as described above.

In each of the above four sets, one sub-word line is selected, and four sub-word lines as shown in FIG. 3C are selected as a whole. Since the four sub-arrays are selected one by one at the same time, in order to avoid the conflict of the sense amplifiers as described above in adopting the Any-to-any type defect relief, The sub-array is composed of only normal word lines.

In this embodiment, in order to employ the defect remedy of the Any-to-any method, in the subarray provided with the redundant word lines, the number of word lines is 32 or 16 in addition to 256 normal word lines. The number of memory cells connected to the bit lines decreases as the number is reduced as in a book. As a result, the amount of signals read out increases due to the charge sharing between the storage charge of the memory cell and the precharge of the parasitic capacitance of the bit line, thereby increasing the read operation margin. And the rescue efficiency can be increased.

For example, in the memory cell in which the information charge held in the capacitor is lost due to the leak current for a short time, the sub-array having the 512 word line configuration becomes a defective cell due to a shortage of the signal amount, and becomes a 256 + 32 word line configuration. In some subarrays, no failure occurs. Since the probability of occurrence of such a defective cell due to the signal amount is reduced in the sub-array provided with the redundant word line, the probability that the memory cell connected to the redundant word line cannot be used due to the defect due to the signal amount is low. The rescue efficiency can be increased.

As described above, when the number of memory cells connected to the bit line is reduced, the load consisting of the parasitic capacitance of the bit line driven by the sense amplifier SA is reduced, and a high-speed read operation can be performed. Therefore, the access to the defective address is detected, and the selection operation of the redundant word line is performed based on the detection result. As a result, the operation of selecting the word line is slowed down. High-speed operation works synergistically,
The above-described operation of selecting the redundant word line can cover the delay, and the time difference between the operation of reading from the memory cell of the normal word line and the operation of reading from the memory cell of the redundant word line can be greatly reduced. High-speed operation becomes possible.

It is also conceivable to form a sub-array of only the redundant word lines. However, when a sub-array having only about 32 or about 64 redundant word lines is provided as described above, the number of memory cells is significantly different from that of a normal sub-array having 512 word lines, and a common sense amplifier constant is used. Therefore, stable operation cannot be performed under the operation timing.

FIG. 5 is a schematic layout diagram showing one embodiment of a sub-array and its peripheral circuits in a dynamic RAM according to the present invention. FIG. 4 shows four sub-arrays SBARY in the memory array shown in FIG.
Are shown as representatives. In FIG. 5, the region where the sub-array SBARY is formed is shaded to distinguish the sub-word driver region, the sense amplifier region, and the cross area provided therearound.

The subarray SBARY is divided into the following four types. That is, assuming that the extending direction of the word lines is the horizontal direction, the first sub-array SBARY arranged at the lower right of FIG. 1 has 512 sub-word lines SWL and 256 complementary bit line pairs. Therefore, 51 corresponding to the 512 sub-word lines SWL
The two sub-word drivers SWD are arranged on the left and right sides of the sub-array in a divided manner into 256 units. 25 above
The 256 sense amplifiers SA provided corresponding to the six pairs of complementary bit lines BL are arranged alternately in addition to the above-described shared sense amplifier system, and are divided into 128 at the top and bottom of the subarray. Be placed.

The second sub-array S arranged at the upper right of FIG.
Although the BARY is not particularly limited, 32 spare (redundant) word lines are provided in addition to 256 regular sub-word lines SWL, and the complementary bit line pairs are composed of 256 pairs. Therefore, the above 256 + 32 sub-word lines SWL
Are subdivided into 144 subword drivers SWD on the left and right sides of the subarray. As described above, 128 sense amplifiers are vertically arranged. That is, one of the 256 pairs formed in the sub-array SBARY arranged above and below the right side.
The 28 pairs of complementary bit lines are commonly connected to the sense amplifier SA interposed therebetween via a shared switch MOSFET.

The third sub-array S arranged at the lower left of FIG.
The BARY includes 512 sub-word lines SWL in the same manner as the right adjacent sub-array SBARY. As described above, 256 sub-word drivers are divided and arranged. Of the 512 sub-arrays SBARY arranged on the lower left and right sides, 256 sub-word lines SWL are commonly connected to 256 sub-word drivers SWD formed in a region sandwiched therebetween. The subarray SBARY arranged at the lower left as described above is provided with four pairs of spare (redundant) bit lines 4R in addition to the 256 pairs of normal complementary bit lines BL. Therefore, the 260 sense amplifiers SA corresponding to the 260 pairs of complementary bit lines BL are divided and arranged in 130 units above and below the subarray.

The fourth sub-array S arranged at the upper left of FIG.
The BARY has 256 regular sub-word lines SWL and 32 spare sub-word lines in the same manner as the right adjacent sub-array SBARY, and has 256 spare regular bit line pairs in addition to the spare pairs as in the lower adjacent sub-array. , Four sub-word drivers are provided, one on each side.
Forty-four are divided and arranged, and the sense amplifiers SA are divided and arranged vertically 130 each.

The main word lines MWL extend in the horizontal direction as described above, one of which is illustratively shown as a representative. The column selection line YS is extended in the vertical direction so that one of them is exemplified as a representative. A sub-word line SWL is arranged in parallel with the main word line MWL, and a complementary bit line BL (not shown) is arranged in parallel with the column selection line YS.

For the above four sub-arrays, 8
The sub-word selection lines FX0B to FX7B are extended to penetrate eight sets (16) of sub-arrays like the main word line MWL. Then, the sub-word selection line F
X0B to FX3B, and FX4B to FX7B
Are extended separately on the upper and lower sub-arrays. Thus, one for two subarrays
Assigning a set of sub-word selection lines FX0B to FX7B,
The reason for extending them on the sub-array is to reduce the size of the memory chip.

On the sub-array, one main word line is provided for eight sub-word lines, and a sub-word select line FX0B is used to select one of the eight sub-word lines. To FX7B. Since the main word line MWL is formed by dividing one of the eight sub word lines SWL formed in accordance with the pitch of the memory cells, the wiring pitch of the main word line MWL is reduced. I have. Therefore, it is relatively easy to form the above-mentioned sub-word selection line between the main word lines by using the same wiring layer as the main word line MWL, with only a slight sacrifice in the looseness of the wiring pitch. .

The sub-word driver SWD of this embodiment
Is obtained by using a selection signal supplied through the sub-word selection line FX0B and the like and a selection signal obtained by inverting the selection signal.
A configuration for selecting one sub-word line SWL is adopted. The sub-word driver SWD is configured to simultaneously select the sub-word lines SWL of the sub-arrays arranged on the left and right of the sub-word driver SWD.

If the one extending in parallel with the main word line MWL is a first sub-word selection line FX0B,
The sub-word selection line driving circuit FXD, which is provided in the upper left cross area and receives a selection signal from the first sub-word selection line FX0B, is arranged above and below 9
A second sub-word selection line FX0 that supplies a selection signal to six (32 + 64) sub-word drivers is provided.
The first sub-word selection line FX0B extends in parallel with the main word line MWL and the sub-word line SWL, while the second sub-word selection line has a column selection line YS and a complementary bit line BL which are orthogonal thereto. The sub word driver area is extended in parallel. The first of the eight
Of the second sub-word selection lines FX0B to FX7B, the second sub-word selection lines FX0 to FX7
The sub-arrays are divided into 0, 2, 4, and 6 and odd FXs 1, 3, 5, and 7, and are allocated to sub-word drivers SWD provided on the left and right of the sub-array SBARY.

The sub word select line driving circuit FXD is
In the same drawing, as shown by a triangle, two pieces are distributed above and below one cross area. That is, as described above, in the upper left cross area, the sub-word selection line driving circuit arranged on the lower side operates the first sub-word selection line F
Two sub-word selection line driving circuits FXD corresponding to X0B and provided in the cross area in the left middle part are disposed above the lower left cross area in correspondence to the first sub-word selection lines FX2B and FX4B. The sub-word selection line driving circuit corresponds to the first sub-word selection line FX6B.

In the upper cross area in the center, the lower sub word select line driving circuit corresponds to the first sub word select line FX1B, and the two sub word select line drive circuits provided in the cross area in the middle center area. Circuit FXD
Correspond to the first sub-word selection lines FX3B and FX5B, and the sub-word selection line driving circuit disposed above the cross area at the lower center corresponds to the first sub-word selection line FX7B. In the upper right cross area, the lower sub word select line drive circuit corresponds to the first sub word select line FX0B, and two sub word select line drive circuits provided in the right middle cross area. FXD is the first sub-word select line FX2B
And the sub-word selection line driving circuit disposed above the cross area at the lower right of FIG. 4 corresponds to the first sub-word selection line FX6B. Thus, in the sub-word driver provided at the end of the memory array,
Since there is no sub-array on the right side, only the left sub-word line SWL is driven.

As in this embodiment, the sub word select line FX is provided in the gap between the main word lines MWL on the sub array.
In the configuration in which B is arranged, a special wiring channel can be made unnecessary, so that arranging eight sub-word selection lines in one sub-array does not increase the size of the memory chip. However, the formation of the sub-word select line driving circuit FXD as described above increases the area of the cross region, which hinders high integration. That is, in the cross area, a switch circuit IOSW provided corresponding to the main input / output line MIO and the local input / output line LIO, a power MOSFET driving a sense amplifier, a shared switch MOS
Driving circuit for driving FET, precharge MOS
This is because there is no area allowance because peripheral circuits such as a drive circuit for driving the FET are formed. For this reason, in the embodiment of FIG. 5, the area increase is suppressed by sharing the sub-word select line driving circuit FXD between the upper and lower sub-arrays.

Among the cross areas, those arranged in the extension direction A of the second sub-word selection lines FX0 to FX6 corresponding to the even numbers have the internal voltage fixed to the sense amplifier as described later. An N-channel power MOSFET Q16 for supplying VDL, an N-channel power MOSFET Q15 for supplying an overdrive power supply voltage VDD, and an N-channel power MOSFET Q14 for supplying a circuit ground potential VSS to the sense amplifier. Is provided.

Of the above-mentioned cross areas, those arranged in the extending direction B of the second sub-word selection lines FX1 to FX7 corresponding to the odd numbers have IO switches (local IO (L
IO) and the switch MOSFE between the main IO (MIO)
T) and MO for precharging and equalizing bit lines
An inverter circuit for turning off the SFET and, although not particularly limited, a ground potential V
N-channel type power MOSF for supplying SS
ET is provided. This N-channel type power MO
The SFET is an N-channel MOSFET amplifying MOSFET configured from both sides of the sense amplifier row.
The ground potential is supplied to the common source line (CSN) of T. That is, the 12 provided in the sense amplifier area
For the eight or 130 sense amplifiers, the N-channel power M provided in the cross area on the A side is used.
OSFET and N provided in the cross area on the B side.
The ground potential is supplied by both of the channel type power MOSFETs.

As described above, the sub-word line drive circuit SWD
Selects the sub-word lines of the sub-array on both the left and right sides with the center as the center. On the other hand, two left and right sense amplifiers are activated corresponding to the sub-word lines of the two selected sub-arrays. That is, when the sub-word line is set to the selected state, the address selection MOSFET is turned on and the charge of the storage capacitor is combined with the bit line charge, so that the sense amplifier is activated to return to the original charge state. This is because a write operation needs to be performed. Therefore, except for the one corresponding to the subarray at the end, the power MOSFET is used to activate the sense amplifiers on both sides of the power MOSFET.
On the other hand, the sub-word line driving circuit S provided on the right or left side of the sub-array provided at the end of the sub-array group
In WD, only the sub-word line of the sub-array is selected, so that the power MOSFET activates only one sense amplifier group corresponding to the sub-array.

The sense amplifier is of a shared sense type, and among the subarrays arranged on both sides of the shared amplifier, the shared switch MOSFET corresponding to the complementary bit line on the side where the subword line is not selected is turned off. As a result, the read signal of the complementary bit line corresponding to the selected sub-word line is amplified, and a rewrite operation of returning the storage capacitor of the memory cell to the original charge state is performed.

FIG. 6 is a circuit diagram of a simplified embodiment from address input to data output centering on the sense amplifier section of the dynamic RAM according to the present invention. In the figure, a sense amplifier 16 sandwiched between two sub-arrays 15 from above and below and a circuit provided in the intersection area 18 are exemplarily shown, and others are shown as block diagrams. The circuit blocks indicated by the dotted lines are indicated by the above-mentioned reference numerals.

The dynamic memory cell is typically exemplified by one provided between the sub-word line SWL provided in the one sub-array 15 and one of the complementary bit lines BL and BLB. Is shown in The dynamic memory cell has an address selection MOS
It comprises an FET Qm and a storage capacitor Cs. The gate of the address selection MOSFET Qm is connected to the sub word line S
The drain of the MOSFET Qm is connected to the bit line BL, and the source is connected to the storage capacitor Cs. The other electrode of the storage capacitor Cs is shared and supplied with the plate voltage VPLT. MOS above
A negative back bias voltage VBB is applied to the substrate (channel) of the FET Qm. Although not particularly limited, the back bias voltage VB
B is set to a voltage such as -1V. The selection level of the sub-word line SWL is a high voltage VPP higher than the high level of the bit line by the threshold voltage of the address selection MOSFET Qm.

When the sense amplifier is operated at the internal step-down voltage VDL, the high level amplified by the sense amplifier and applied to the bit line is equal to the internal voltage VD
The level is set to L level. Therefore, the high voltage VPP corresponding to the word line selection level is set to VDL + Vth + α. A pair of complementary bit lines BL and BLB of the sub-array provided on the left side of the sense amplifier are arranged in parallel as shown in FIG. These complementary bit lines BL and BLB are connected to input / output nodes of a unit circuit of the sense amplifier by shared switch MOSFETs Q1 and Q2.

The unit circuit of the sense amplifier comprises N-channel type amplifying MOSFETs Q5, Q6 and P-channel type amplifying MOSFETs Q7, Q8, whose gates and drains are cross-connected to form a latch. The sources of the N-channel MOSFETs Q5 and Q6 are connected to a common source line CSN. The sources of the P-channel MOSFETs Q7 and Q8 are connected to a common source line CS.
Connected to P. Power switch MOSFETs are connected to the common source lines CSN and CSP, respectively. Although not particularly limited, an N-channel type amplification MOS
Common source line C to which the sources of FETs Q5 and Q6 are connected
An operating voltage corresponding to the ground potential is applied to SN by an N-channel type power switch MOSFET Q14 provided in the cross area 18.

Although not particularly limited, the common source line CSP to which the sources of the P-channel type amplification MOSFETs Q7 and Q8 are connected is connected to the N-channel type power MOSFET for overdrive provided in the cross area 18.
An SFET Q15 and an N-channel power MOSFET Q16 for supplying the internal voltage VDL are provided.
The power supply voltage VDD supplied from an external terminal is used for the overdrive voltage, although there is no particular limitation. Alternatively, the power supply voltage VDD of the sense amplifier operating speed
VPP is applied to the gate to reduce the dependency,
The voltage may be slightly reduced as the voltage is obtained from the source of the N-channel MOSFET whose power supply voltage VDD is supplied to the drain.

The N-channel type power MOSFET
The sense amplifier overdrive activation signal SAP1 supplied to the gate of Q15 is
Activation signal SAP supplied to the gate of SFET Q16
2, and SAP1 and SAP2 are set to a high level in time series. Although not particularly limited, SAP1
And the high level of SAP2 is a signal of the boosted voltage VPP level. That is, the boost voltage VPP is about 3.8 V, so that the N-channel MOSFET Q15 can be sufficiently turned on. MOSFET Q15
Is turned off (signal SAP1 is at low level),
A voltage corresponding to the internal voltage VDL can be output from the source side by turning on the SFET Q16 (the signal SAP2 is at a high level).

An equalizing MOSF for short-circuiting a complementary bit line is provided at the input / output node of the unit circuit of the sense amplifier.
ETQ11 and switch MOSFETs Q9 and Q10 for supplying half precharge voltage VBLR to complementary bit lines
A precharge (equalize) circuit is provided. The gates of these MOSFETs Q9 to Q11 are commonly supplied with a precharge signal PCB. Although not shown, a driver circuit for forming the precharge signal PCB is provided with an inverter circuit in the cross area so that the rise and the rise are made faster. That is, at the start of the memory access, prior to the word line selection timing, the MOSFE which constitutes the precharge circuit through the inverter circuits distributed in each cross area.
TQ9 to Q11 are switched at high speed.

The cross area 18 includes an IOSW (a switch MOSFE for connecting a local IO and a main IO).
T 19, Q20) is placed. Further, other than the circuit shown in FIG. 4, if necessary, a half precharge circuit for the common source lines CSP and CSN of the sense amplifier, a half precharge circuit for the local I / O line LIO, and a VDL precharge circuit for the main IO , Shared distributed signal lines SHR and SHL are also provided.

The unit circuit of the sense amplifier is connected to similar complementary bit lines BL and BLB of the sub-array 15 on the lower side of the figure via shared switch MOSFETs Q3 and Q4. For example, when the sub-word line SWL of the upper sub-array is selected, the upper shared switch MOSFETs Q1 and Q2 of the sense amplifier are turned on, and the lower shared switch MOSFETs Q3 and Q4 are turned off. The switch MOSFETs Q12 and Q13 constitute a column switch circuit, and the selection signal Y
When S is set to the selected level (high level), the input terminal is turned on, and the input / output nodes of the unit circuit of the sense amplifier and the local input / output lines LIO1 and LIO1B, LIO2, LIO
2B or the like.

As a result, the input / output node of the sense amplifier is connected to the upper complementary bit lines BL and BLB to amplify the small signal of the memory cell connected to the selected sub-word line SWL, Circuit (Q
12 and Q13) through the local input / output lines LIO1, L
Communicate to IO1B. The local input / output lines LIO1, L
IO1B extends along the sense amplifier row, that is, in the horizontal direction in FIG. The local input / output line LI
O1 and LIO1B are the N provided in the cross area 18.
IO consisting of channel type MOSFETs Q19 and Q20
The input terminals of the main amplifier 61 are connected to main input / output lines MIO and MIOB via a switch circuit. Note that the IO switch circuit is provided with a selection signal IOSW
As a result, a CMOS switch is obtained in which a P-channel MOSFET is connected in parallel to each of the N-channel MOSFETs Q19 and Q20 as described later.

Although not particularly limited, the column switch circuit includes two pairs of complementary bit lines BL, BLB and two pairs of local input / output lines LIO1, LI in response to one selection signal YS.
O1B is connected to LIO2 and LIO2B. Therefore, in the sub-array selected by one main word line selecting operation, a total of four pairs of complementary bit lines are selected by the two pairs of column switch circuits provided corresponding to the sense amplifiers provided on both sides thereof. Will be. In the burst mode of the synchronous DRAM, the column selection signal YS is switched by a counter operation, and the connection between the local input / output lines LIO1 and LIO1B and the complementary bit lines BL and BLB of the sub-array is sequentially switched.

The address signal Ai is supplied to the address buffer 5
1 is supplied. The address buffer operates in a time-division manner to receive the X address signal and the Y address signal.
The X address signal is supplied to the predecoder 52, and a selection signal for the main word line MWL is formed via the main row decoder 11 and the main word driver 12. Since the address buffer 51 receives the address signal Ai supplied from the external terminal, it is operated by the power supply voltage VDD supplied from the external terminal, and the predecoder is operated by the step-down voltage VPERI.
The main word driver 12 is operated by the boost voltage VPP. Column decoder (driver) 53
Receives the Y address signal supplied by the time-division operation of the address buffer 51 and receives the selection signal Y.
Form S.

The main amplifier 61 has a step-down voltage VPE
The signal is output from the external terminal Dout through the output buffer 62 operated by the RI and operated by the power supply voltage VDD supplied from the external terminal. The write signal input from the external terminal Din is taken in through the input buffer 63, and is passed through a write amplifier included in the main amplifier 61 in FIG.
A write signal is supplied to IO and MIOB. The input section of the output buffer is provided with a level shift circuit and a logic section for outputting the output signal in synchronization with a timing signal corresponding to the clock signal.

Although not particularly limited, the power supply voltage VDD supplied from the external terminal is set to 3.3 V, the step-down voltage VPERI supplied to the internal circuit is set to 2.5 V, and the operating voltage VDL of the sense amplifier is set. Is set to 2.0V. Then, the word line selection signal (boosted voltage)
It is set to 3.6V. Bit line precharge voltage VBL
R is set to 1.0 V corresponding to VDL / 2, and the plate voltage VPLT is also set to 1.0 V. And the substrate voltage V
BB is set to -1.0V.

In the above configuration, for example, in the embodiment shown in FIG. 2A, the number of sense amplifier rows is increased by one in the embodiment shown in FIG. 2B only increases by two), and in the embodiment of FIG. 2B only increases by two, so that the substantial increase in chip size can be suppressed to be small. Even in a configuration in which the length and width are reversed as in the third embodiment, an increase in chip size does not cause a problem similarly.

The functions and effects obtained from the above embodiment are as follows. (1) In a dynamic RAM in which a plurality of sub-arrays are provided in a complementary bit line direction, the number of normal word lines provided in a sub-array in which redundant word lines are provided is
By setting the number of normal word lines in the sub-array provided in the direction of the complementary bit lines and not provided with the redundant word lines to be less than the number of normal word lines, the rate of occurrence of defects in the redundant sub-array is significantly reduced, and the relief efficiency can be increased. At the same time, there is an effect that the operation can be speeded up.

(2) A shared sense amplifier is provided,
In a dynamic RAM in which a plurality of sub-arrays are provided in a complementary bit line direction, a plurality of redundant word lines are concentrated and arranged on two or four sub-arrays among the plurality of sub-arrays arranged in the complementary bit line direction. By setting the number of normal word lines provided in the sub-array in which the redundant word lines are arranged to be smaller than the number of normal word lines in the sub-array provided in the direction of the complementary bit lines and in which the redundant word lines are not arranged. This has the effect of significantly reducing the rate of occurrence of defects in the redundant subarray, increasing the rescue efficiency, and increasing the speed of operation.

(3) By arranging the redundant word line substantially in the center of the sub-array including the redundant word line, the redundant memory array can be manufactured under stable manufacturing conditions with a smaller step than the end of the sub-array. The effect that high yield can be achieved is obtained.

(4) A plurality of the word lines are divided in a main word line and an extension direction of the main word line, and a plurality of the word lines are arranged in a bit line direction crossing the main word line. A plurality of sub-word lines to which address selection terminals of dynamic memory cells are connected, and a plurality of sub-arrays in which a sub-word line driving circuit is divided and arranged at both end sides of the plurality of sub-word line arrays. Despite high integration, higher yield can be achieved by alleviating the wiring repetition pitch of the main word lines by being formed so as to be surrounded by the sub word line drive circuit row and the plurality of sense amplifier rows. The effect is obtained.

(5) A plurality of the sub-arrays are arranged in the word line direction and the bit line direction, respectively, to constitute a memory array. In the memory array, the upper part of the plurality of sub-arrays arranged in the complementary bit line direction is used. By allocating a subarray in which the redundant word lines are arranged except for two subarrays adjacent to each other at the boundary between the half and the lower half, the upper half and the lower half are adopted while adopting a half-independent Any-to-any method. The advantage is that half the word lines can be selected simultaneously.

(6) By providing a refresh mode in which the upper half and lower half memory cells of the memory array are simultaneously refreshed in the above (4), the effect that the refresh test in the test mode can be performed in a short time can be obtained.

(7) The number of normal word lines in the small number of subarrays provided with the redundant word lines is 256, and the number of normal word lines in the overwhelming number of subarrays not provided with the redundant word lines is 512. By doing so, it is possible to obtain an effect that a high yield and a high speed of the dynamic RAM can be realized while suppressing an increase in area.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention of the present application is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, in the dynamic RAM shown in FIG. 1, for example, the configurations of the memory array, the sub-array, and the sub-word driver may employ various embodiments, or may be a word shunt system without using a sub-word driver.

In the configuration in which the number of normal word lines of the sub-array is 512, the memory array is arranged one word line in the word line direction.
The sub-array may be divided into six, and the normal bit line pairs of the sub-array may be 256 pairs, or the sub-array may be divided into eight as 512 pairs similarly to the word lines. Alternatively, the sub-array including only the normal word lines has 256 word lines, and the sub-array having the redundant word lines has 128 normal word lines, which is half the number of the normal word lines, and 16 or 8 redundant word lines are provided. It may be. The subarrays arranged in the bit line direction are divided into two types. One of the overwhelming majority is only the normal word lines, and the relatively small number of subarrays provided with the redundant word lines are defective memory cells caused by the signal amount. Can be reduced, and the number of normal word lines may be reduced to such an extent that the amplification operation by the sense amplifier becomes faster.

The dynamic RAM according to the present invention
It may be built in a digital integrated circuit such as a one-chip microcomputer. The present invention
It can be widely used for a dynamic RAM having a redundancy function.

[0080]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a dynamic RAM in which a plurality of sub-arrays are provided in the direction of complementary bit lines, the number of normal word lines provided in the sub-array in which redundant word lines are provided is determined by the number of normal word lines provided in the direction of the complementary bit lines. Is set to be smaller than the number of normal word lines in the subarray where no array is arranged, the failure occurrence rate in the redundant subarray is significantly reduced, the rescue efficiency can be increased, and the operation can be speeded up.

[Brief description of the drawings]

FIG. 1 is a schematic layout diagram showing one embodiment of a dynamic RAM to which the present invention is applied.

FIG. 2 is a memory mat configuration diagram showing one embodiment of a dynamic RAM according to the present invention;

FIG. 3 is a memory array configuration diagram showing another embodiment of the dynamic RAM according to the present invention.

FIG. 4 is a configuration diagram of a memory mat showing one embodiment of the dynamic RAM of FIG. 3;

FIG. 5 is a schematic layout diagram showing one embodiment of a sub-array and its peripheral circuits in a dynamic RAM according to the present invention.

FIG. 6 is a circuit diagram showing a simplified embodiment from address input to data output centering on the sense amplifier section of the dynamic RAM according to the present invention.

[Explanation of symbols]

10: memory chip, 11: main row decoder area,
12: Main word driver area, 13: Column decoder area, 14: Peripheral circuit, bonding pad area, 1
5, 151, 152: Meseli cell array (sub array), 16: Sense amplifier area, 17: Sub word driver area, 18: Intersection area (cross area), # 1 to #
20: Sub-array, SA: Sense amplifier, 51: Address buffer, 52: Predecoder, 53: Decoder, 6
1 Main amplifier, 62 Output buffer, 63 Input buffer, Q1 to Q20 MOSFET.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor: Red 22 Saki Hiroshi 5-22-1, Josuihoncho, Kodaira-shi, Tokyo Inside Hitachi Cho LSI Systems Co., Ltd.

Claims (8)

[Claims] A gate connected to a corresponding word line;
An address selection MOSFET having one source and drain connected to one of the corresponding complementary bit lines, and a storage capacitor having a storage node connected to the other source and drain of the address selection MOSFET and a predetermined voltage applied to the other. Wherein the complementary bit line comprises a plurality of complementary bit line pairs, one of which has an input / output terminal of the dynamic memory cell connected thereto, and the plurality of word lines and the plurality of A sub-array is constituted by a pair of complementary bit lines and a plurality of the dynamic memory cells provided at intersections thereof. A plurality of the sub-arrays are provided, and a plurality of redundant words are provided in the plurality of sub-arrays provided in the direction of the complementary bit line. Having at least one subarray in which the lines are arranged, The number of normal word lines provided in the sub-array on which the redundant word lines are provided is set to be smaller than the number of normal word lines provided in the sub-array on which the redundant word lines are not provided. A dynamic RAM. 2. A gate is connected to a corresponding word line,
An address selection MOSFET having one source and drain connected to one of the corresponding complementary bit lines, and a storage capacitor having a storage node connected to the other source and drain of the address selection MOSFET and a predetermined voltage applied to the other. Wherein the complementary bit line comprises a plurality of complementary bit line pairs, one of which has an input / output terminal of the dynamic memory cell connected thereto, and the plurality of word lines and the plurality of A sub-array is constituted by the complementary bit line pairs and the plurality of dynamic memory cells provided at the intersections thereof, and the sub-arrays are arranged such that sense amplifiers are distributed to both ends of at least the plurality of complementary bit line pairs. A plurality of sub-arrays that are divided and arranged in the complementary bit line direction A), a plurality of redundant word lines are concentratedly arranged in a small number of sub-arrays, and the number of normal word lines provided in the sub-array in which the redundant word lines are arranged is set in the complementary bit line direction. A dynamic RA characterized by being set to be smaller than the number of normal word lines in a large number of subarrays in which no redundant word lines are arranged.
M. 3. The word line has a length that is divided with respect to a main word line and an extension direction of the main word line, and a plurality of the word lines are arranged in a bit line direction that intersects with the main word line. A plurality of sub-word lines connected to address selection terminals of a plurality of dynamic memory cells, the plurality of sub-word lines, the plurality of complementary bit line pairs, and the plurality of dynamic memory cells provided at intersections thereof. A sub-array is configured, and sub-word line driving circuits are divided and arranged at both ends of the plurality of sub-word line arrays, and one of the sub-arrays includes the plurality of sub-word line driving circuit columns and the plurality of senses. 3. The die according to claim 1, wherein the die is formed so as to be surrounded by an amplifier array. Namic RAM. 4. A memory array comprising a plurality of sub-arrays each arranged in a word line direction and a bit line direction, and a plurality of sub-arrays arranged in the complementary bit line direction in the memory array. 3. The dynamic RAM according to claim 2, wherein a sub-array in which the redundant word lines are arranged is allocated except for two sub-arrays adjacent to each other at a boundary between the upper half and the lower half. 5. The dynamic RAM according to claim 4, wherein said memory array has a refresh mode in which upper half and lower half memory cells are simultaneously refreshed. 6. The memory array includes four memory chips.
Bonding pads and peripheral circuits are formed in the longitudinal center of the memory chip, word lines are extended in the longitudinal direction of the memory chip, and complementary bit lines are extended in the lateral direction of the memory chip. The dynamic RAM according to claim 5, wherein: 7. The memory array includes four memory chips.
Bonding pads and peripheral circuits are formed at the longitudinal center of the memory chip, word lines are extended in the lateral direction of the memory chip, and complementary bit lines are extended in the longitudinal direction of the memory chip. The dynamic RAM according to claim 5, wherein: 8. The sub-array according to claim 2, wherein the number of normal word lines of the sub-array provided with the redundant word lines is 256, and the number of normal word lines of the sub-array not provided with the redundant word lines is provided. A dynamic RAM, wherein the number of lines is 512.