JPH1186549A - Dynamic RAM - Google Patents

Abstract

(57) [Problem] To provide a dynamic RAM in which the information retention characteristics of memory cells are improved and high-speed operation is realized. In a dynamic RAM of the BSG system, an internal voltage lower than a precharge voltage and higher than a boosted ground level is formed, and an operating voltage on a low level side of a sense amplifier in a period before a word line is selected. Immediately before the word line is deselected, the internal voltage is switched to the boosted ground level to set the low level of the bit line to the boosted ground level, and the direct sense is applied to the column switch section. Provide an amplifier.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic RAM (random access memory), and more particularly to a technology effective when used in a sense amplifier using a boosted sense ground (BSG) system.

[0002]

2. Description of the Related Art The breakdown voltage of a MOSFET decreases as it is miniaturized. For this reason, the miniaturized MOSF
In the circuit constituted by ET, it is necessary to lower the operating voltage. In this case, since the gate voltage supplied to the gate also becomes low, it is necessary to lower the threshold voltage so that a desired current flows even with the lowered gate voltage. However, if the threshold voltage is set low,
A leak current (hereinafter referred to as a sub-threshold leak current) flowing when the gate and the source are turned off by equalizing the voltage between the gate and the source increases exponentially.

In a dynamic memory cell, in a memory cell in which a word line is not selected, the holding time of an information storage capacitor holding a high level due to the above-described subthreshold leak current is shortened, and the refresh cycle is shortened. And that increases the overall current consumption. As a method of reducing such a leak current, a boosted sense ground (B
SG) method. In this method, the low level output of the sense amplifier is transmitted to the bit line as a boosted ground level of about 0.5V. In this configuration, since a reverse bias voltage is applied between the gate and the source of the address selection MOSFET of the memory cell by the boosted ground level, the sub-threshold leakage current can be reduced. In the BSG method, the low level of the sense amplifier is raised, so that the amount of charge stored in the capacitor decreases. Therefore,
Japanese Unexamined Patent Publication No. Hei 7 (1996) -1995 discloses a method in which the low level of the sense amplifier is lowered to the ground potential before the word line is deselected, and the sense amplifier is amplified in two stages to secure the signal level.
85662.

[0004]

When the bit line is set to the low level such as the ground potential as described above, the potential between the gate and the source of the address selection MOSFET is temporarily set to the same potential in the memory cell where the word line is not selected. As a result, a relatively large sub-threshold leak current flows, and the high level held in the storage capacitor is reduced. That is, an attempt to increase the amount of stored information in the selected memory cell has the adverse effect of increasing the sub-threshold leakage current in the non-selected memory cell. Therefore, the present inventors have considered a dynamic RAM in which the reading operation is sped up while improving the information holding characteristics of the storage capacitor by utilizing the two-stage sensing operation of the sense amplifier as described above.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a dynamic RAM capable of improving the information retention characteristics of a memory cell and realizing high-speed operation.
Is to provide. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0006]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in the dynamic RAM of the BSG system, an internal voltage lower than the precharge voltage and higher than the boosted ground level is formed, and in the period before the word line is selected, the internal voltage is set as the low-level operating voltage of the sense amplifier. Immediately before the word line is deselected, the internal voltage is switched to the boosted ground level to set the low level of the bit line to the boosted ground level, and a direct sense amplifier is connected to the column switch section. Provide.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a conceptual diagram for explaining the present invention. FIG. 1A shows a selected memory cell and an unselected memory cell, and FIG. 1B shows a characteristic diagram of a subthreshold leak current Ioff in an address selection MOSFET. When the potential of the bit line is set to the low level corresponding to the boosted ground level in accordance with the amplified signal of the sense amplifier in the memory cell in which the word line is selected as described above, the low-level rewrite operation is performed on the selected memory cell. It is something to be done. However, in the memory cells in which the word line is at the non-selection level during that time, the address selection MO is not used.
Since the gate and the source of the SFET are reverse-biased only at a relatively small voltage corresponding to the boosted sense level VBSG2, the sub-threshold leakage current Ioff is relatively increased as shown at the operating point B in FIG. It acts to lose the high data of the capacitor.

Therefore, in the present invention, the sense amplifier performs two-stage amplification. In other words, the operating voltage on the low level side of the sense amplifier is lowered by the half precharge voltage of the bit line, a predetermined voltage VBSG1 larger than the boosted sense level VBSG2 is used, and when the word line is selected, the voltage VBSG1 is used. The sense amplifier performs an amplifying operation. By doing so, the sub-threshold leak current Ioff decreases exponentially (Log) like the operating point A in FIG. 1B, and the data retention characteristics of the unselected memory cells can be greatly improved. . However, in this state, the voltage difference VBS
Since the signal charge amount on the low level side decreases by G1−VBSG2, the operating voltage on the low level side of the sense amplifier is changed to VBS just before the selected word line is deselected.
Returning from G1 to the original boosted sense level VBSG2, the low level written to the storage capacitor is increased. At this time, the potential of the bit line changes from VBSG1 to VBSG2, and the unselected word line can be set to a potential lower than VSS (negative potential) by coupling with the word line. It acts in a direction to improve the characteristics.

Immediately after the word line is set to the selected state as described above, the signal level on the low level side of the sense amplifier is reduced corresponding to the voltage VBSG1, and the read operation itself is delayed. Therefore, in the present invention, a direct sense amplifier as described below is added to speed up the read operation of the dynamic memory cell.

FIG. 2 is a circuit diagram showing one embodiment of a sense amplifier, a write circuit, and a read amplifier circuit (direct sense amplifier) in a dynamic RAM according to the present invention. In the figure, a P-channel type M
OSFETs are distinguished from N-channel MOSFETs by the addition of arrows to their channel portions. This is the same in other circuit diagrams.

A pair of complementary bit lines BL and / BL are arranged in parallel as shown in FIG. 1 and are appropriately crossed as necessary to balance the bit line capacitance. These complementary bit lines BL and / BL are connected to an input / output node of a sense amplifier. The sense amplifier includes N-channel type MOSFETs Q5 and Q6 and a P-channel type MOS in which a gate and a drain are cross-connected and latched.
It comprises FETs Q7 and Q8. N-channel MO
The sources of the SFETs Q5 and Q6 are connected to a common source line CSN.
Connected to. P-channel MOSFETs Q7 and Q8
Are connected to a common source line CSP. Although not shown in the figure, a power switch MOSFET of a P-channel type MOSFET is provided for the common source line CSP, and an internal step-down voltage VDL formed by an internal voltage generating circuit is supplied. N-channel type MOSFETQ
An N-channel MOSFET (not shown) is also provided on the common source line CSN corresponding to 5 and Q6, and two-stage operating voltages VBSG1 and VBSG2 formed by the internal voltage generating circuit are supplied. The switch MOSFET that supplies these voltages is included in the two-stage sense control circuit.

Although not shown, a MOSFET for short-circuiting the complementary bit line is provided at the input / output node of the sense amplifier.
And a precharge circuit comprising a switch MOSFET for supplying a half precharge voltage to the complementary bit line. The gates of these MOSFETs are supplied with a precharge signal in common, and are turned on when the word line is deselected to set the bit lines BL and / BL to a precharge voltage.

In this embodiment, a direct sense amplifier is provided for substantially compensating for a decrease in signal level due to the two-stage sensing operation of the sense amplifier and speeding up the reading operation. The direct sense amplifier includes an amplifying MOSFET Q receiving voltages of complementary bit lines BL and / BL.
12, Q13 and the amplification MOSFETs Q12, Q13
, And select switches MOSFETs Q32 and Q33 each having a gate connected to a column select line YS. The amplifying MOSFETs Q12 and Q13 have their sources supplied with the ground potential VSS. Although not particularly limited, the read-only lines / RIO and RIO are provided with a precharge circuit for precharging to the operating voltage VDL, and the read-only lines / RIO or RIO corresponding to the high level after the amplification MOSFETs Q12 and Q13.
Is largely pulled down to a low level, and the amplified signal is transmitted to an input of a main amplifier (not shown).

Even if the amplified signal of the sense amplifier has a relatively small signal amplitude such as the high level (VDL) and the low level (VBSG1) as described above, it is amplified by inserting such a direct sense amplifier. And the direct sense amplifier has a high input impedance, and its operation does not cause a potential change on the bit lines BL and / BL, so that it does not adversely affect the amplification operation of the sense amplifier. It is possible to transmit the read signal to the main amplifier by performing the read operation as far as possible, so that the read time can be shortened.

As described above, the read-only lines / RIO and R
In response to the provision of the IO, the write-only line WI
O and / WIO are provided. This write-only line WIO
In order to adjust the high level and the low level of the write signal transmitted from / WIO to VDL and VBSG2, a write buffer (not shown) is operated from the voltages VDL and VBSG2. As a result, a high-level write signal corresponding to the VDL and a low-level write signal corresponding to VBSG2 are transmitted to the write-only lines WIO and / WIO. That is, the write-only lines WIO and / WIO are connected to the switch MOSFETs Q17 and Q18 which are turned on by the write pulse WP,
Column selection MOSFETs Q15 and Q16 switch-controlled by the column selection line transmitted to the column selection line YS
To the bit lines BL and / BL. As a result, the potentials of the bit lines BL and / BL change according to the signals of the read-only lines / RIO and RIO, and are written to the selected memory cell.

FIG. 3 is a schematic timing chart for explaining a read operation of the dynamic RAM according to the present invention. In the figure, a sense amplifier control signal SAP for supplying a word line WL directly related to the present invention, an operating voltage corresponding to VDL to the sense amplifier, and a two-stage operating voltage VBSG1 and VBSG2 to the sense amplifier. , SAN1, SAN2 and complementary bit lines BL, / BL are exemplarily shown as representatives.
A row (RAS) address selecting operation is started by a low level of a row address strobe signal (not shown). That is, a row address signal is fetched in response to the change of the row address strobe signal to a low level, and the address signal fetched by the decoder is decoded. At the same time, the precharge operation is completed and the complementary bit lines BL and / BL maintain the precharge level in a high impedance state.

Based on the result of the decoding, the word line WL is set to the selected level of the boosted high level VCH. The selection level VCH is a boosted voltage that is higher than the internal voltage VDL by an effective threshold voltage of the address selection MOSFET of the memory cell. By the operation of selecting the word line WL, the complementary bit lines BL, / B
The memory cell selected from L is connected, and the potential of the bit line rises to, for example, a high level according to the storage charge of the memory cell. As described above, when a minute potential change according to the storage charge of the memory cell appears on the bit line, the activation signal SAP of the sense amplifier is set to the low level and SAN1 is set to the high level, and the amplification operation of the sense amplifier is started. That is, VD is applied to the CMOS latch constituting the sense amplifier.
L and VBSG1 are provided as operating voltages. As a result, the bit lines BL and / BL coupled to the input / output nodes of the sense amplifier are initially amplified to a high level corresponding to VDL and a low level corresponding to VBSG1 according to a minute read voltage from the memory cell.

In the read operation, a selected bit line is determined by a column-based selecting operation (not shown), and the complementary bit lines BL, / BL amplified by the sense amplifier are read.
Is further amplified by the direct sense amplifier, transmitted to the main amplifier through the read-only lines RIO and / RIO, and output from an external terminal through a data output circuit. Even if the potential difference between the complementary bit lines BL and / BL is limited to a relatively small voltage like VDL-VBSG1 by inserting such a direct sense amplifier, the reading speed can be increased without being affected by the difference. Becomes

In this state, the low-level potential of bit line BL or / BL is maintained at a relatively high voltage corresponding to voltage VBSG1. Therefore, in a memory cell in which the word line is set to a non-selection level such as the ground potential, a relatively large reverse bias voltage such as -VBSG1 is applied between the gate and the source of the address selection MOSFET. Only a small sub-threshold leakage current Ioff corresponding to the operating point A in FIG. 1B flows, and the data retention characteristics of the unselected memory cells can be improved.

Before the selected word line is switched to the non-selected state, the operating voltage on the low level side of the sense amplifier is changed from the voltage VBSG1 before the selected word line is switched to the non-selected state. Is switched to the voltage VBSG2 corresponding to the boosted sense ground level. As a result, the low level of the bit line also changes to the voltage VBSG2, and the original storage charge is written to the memory cell. The timing at which the low-level operation voltage of the sense amplifier is switched from the voltage VBSG1 to the voltage VBSG2 corresponding to the boosted sense ground level is not particularly limited, but the signal SAN1 is changed due to the change of the row address strobe signal to the high level. It is sufficient to switch from the high level to the low level, change the signal SAN2 from the low level to the high level, and change the signal SAN2 from the high level to the low level by changing the word line WL to the low level.

Although not shown, after the activation signals SAP and SAN2 of the sense amplifier are respectively reset, a precharge signal is generated to short-circuit the complementary bit lines BL and / BL to perform a precharge operation. As a result, the complementary bit lines BL and / BL become (VDL-VBSG2) /
2 is set to a half precharge voltage. Although not particularly limited, the common source line CS of the sense amplifier
N and CSP are precharged in the same manner as described above.

FIG. 4 is a timing chart for explaining the write operation of the dynamic RAM according to the present invention. In the same figure, the word line WL directly related to the present invention and the sense amplifier
, And sense amplifier control signals SAP, SAN1, SAN2 and complementary bit lines BL, / BL, which supply the operating voltage corresponding to the above and the two-stage operating voltage consisting of VBSG1 and VBSG2 to the sense amplifier, are exemplarily shown as representatives. ing. Similarly to the above, the row address signal is taken in by the row level of the row address strobe signal, and the address signal taken in by the decoder is decoded. At the same time, the precharge operation is completed and the complementary bit lines BL and / BL maintain the precharge level in a high impedance state.

Based on the result of the decoding, the word line WL is set to the selected level of the boosted high level VCH. The selection level VCH is a boosted voltage that is higher than the internal voltage VDL by an effective threshold voltage of the address selection MOSFET of the memory cell. By the operation of selecting the word line WL, the complementary bit lines BL, / B
The memory cell selected from L is connected, and the potential of the bit line rises to, for example, a high level according to the storage charge of the memory cell. As described above, when a minute potential change according to the storage charge of the memory cell appears on the bit line, the activation signal SAP of the sense amplifier is set to the low level and SAN1 is set to the high level, and the amplification operation of the sense amplifier is started.

VDL and VBSG1 are supplied as operating voltages to the CMOS latch constituting the sense amplifier. As a result, the bit lines BL and / BL coupled to the input / output nodes of the sense amplifier are initially amplified to a high level corresponding to VDL and a low level corresponding to VBSG1 according to a minute read voltage from the memory cell. At the timing when the column address strobe signal changes to low level, if the write enable signal is at low level, it is determined that the write operation is performed, and the write operation is performed on the bit lines BL, BL corresponding to the selected memory cell by the column-related selection operation. Is conveyed. This sense amplifier determines the potential of the bit lines BL, BL according to the write signal.

In this state, the low-level potential of the bit line BL or / BL remains at the voltage VBSG even for the above-described write operation, as in the above-described read operation.
1 is maintained at a relatively high voltage. Therefore, in a memory cell in which the word line is set to a non-selection level such as the ground potential, a relatively large reverse bias voltage such as -VBSG1 is applied between the gate and the source of the address selection MOSFET. Only a small sub-threshold leakage current Ioff corresponding to the operating point A in FIG. 1B flows, and the data retention characteristics of the unselected memory cells can be improved.

Before the selected word line is switched to the non-selected state, the operating voltage on the low level side of the sense amplifier is changed from the voltage VBSG1 to the original level in order to increase the low-level storage charge written in the capacitor of the memory cell. The voltage is switched to the voltage VBSG2 corresponding to the boosted sense ground level. As a result, the low level of the bit line also changes to the voltage VBSG2, and the original write charge is written to the memory cell. The operating voltage on the low level side of the sense amplifier is changed from the voltage VBSG1 to the voltage VBS corresponding to the boosted sense ground level.
As the timing for switching to G2, the signal SAN1 is switched from high to low level by changing the row address strobe signal to high level as described above, the signal SAN2 is changed from low to high level, and the word line WL is changed to low level. , The signal SAN2 may be changed from the high level to the low level.

Although not shown, after the activation signals SAP and SAN2 of the sense amplifier are respectively reset, a precharge signal is generated to short-circuit the complementary bit lines BL and / BL to perform a precharge operation. As a result, the complementary bit lines BL and / BL become (VDL-VBSG2) /
2 is set to a half precharge voltage. Although not particularly limited, the common source line CS of the sense amplifier
N and CSP are precharged in the same manner as described above, and the write cycle ends.

FIG. 5 is a schematic layout diagram of one embodiment of the dynamic RAM according to the present invention.
In the figure, of the circuit blocks constituting the dynamic RAM, a portion related to the present invention is shown so as to be understood. It is formed on one semiconductor substrate.

In this embodiment, although not particularly limited, the memory array is divided into four as a whole. Two memory arrays are divided into two on the left and right sides in the longitudinal direction of the semiconductor chip, and an address input circuit, a data input / output circuit, an input / output interface circuit including a bonding pad row, and the like are provided in the central portion 14. Column decoder regions 13 are arranged in portions of both sides of the central portion 14 in contact with the memory array. As described above, in each of the four memory arrays divided into two on the left and right sides and two on the upper and lower sides with respect to the longitudinal direction of the semiconductor chip, the main row decoder area 11 is located at the upper and lower central parts in the longitudinal direction. Provided. Main word driver regions 12 are formed above and below the main row decoder, and drive the main word lines of the vertically divided memory array.

The above memory cell array (subarray) 15
Are formed so as to be surrounded by the sense amplifier region 16 and the sub-word driver region 17 with the memory cell array 15 interposed therebetween, as shown in the enlarged view. An intersection between the sense amplifier region and the sub-word driver region is an intersection region (cross area) 18. The sense amplifiers provided in the sense amplifier region 16 are configured by a shared sense method, and except for the sense amplifiers arranged at both ends of the memory cell array, complementary bit lines are provided on the left and right around the sense amplifier. Selectively connected to the complementary bit lines of the memory cell array.

As described above, the memory arrays divided into four on the left and right sides in the longitudinal direction of the semiconductor chip are arranged in groups of two. In the two memory arrays thus arranged in pairs, the main row decoder region 11 and the main word driver 12 are arranged in the center. This main row decoder 11
It is provided in common corresponding to the two memory arrays which are divided up and down around the center. The main word driver 12 generates a selection signal of a main word line extended so as to penetrate the one memory array. Also,
The main word driver 12 is also provided with a driver for selecting a sub-word, and extends in parallel with the main word line to form a selection signal for the sub-word selection line, as described later.

Although not shown, one memory cell array (sub-array) 15 shown as an enlarged view has 256 sub-word lines and 256 pairs of complementary bit lines (or data lines) orthogonal thereto. In the one memory array, 16 memory cell arrays (sub arrays) 15 are provided in the word bit line direction. Therefore, the sub word lines as a whole are provided for about 4K, and 8 sub word lines are provided in the word line direction. The bit line is about 2
K are provided. Since eight such memory arrays are provided in total, a large storage capacity such as 8 × 2K × 4K = 64 Mbits is provided.

The one memory array is divided into eight in the main word line direction. A sub-word driver (sub-word line driving circuit) 17 is provided for each of the divided memory cell arrays 15. The sub-word driver 17 is divided into の 長 of the length of the main word line, and forms a sub-word line selection signal extending in parallel with the length. In this embodiment, in order to reduce the number of main word lines, in other words, to reduce the wiring pitch of the main word lines, there is no particular limitation. Are arranged four sub-word lines. In order to select one sub-word line from among the sub-word lines divided into eight in the main word line direction and four in the complementary bit line direction, a sub-word selection driver is used. Be placed. This sub-word selection driver is extended in the arrangement direction of the sub-word drivers.
A selection signal for selecting one of the sub-word selection lines is formed.

Focusing on the one memory array, 1
One sub-word selection line is selected in a sub-word driver corresponding to one memory cell array including a memory cell to be selected among eight memory cell arrays allocated to one main word line, resulting in one main word One sub-word line is selected from 8 × 4 = 32 sub-word lines belonging to the line. As described above, 2K (2048) memory cells are provided in the main word line direction.
/ 8 = 256 memory cells are connected.
Although not particularly limited, in a refresh operation (for example, a self-refresh mode), eight sub-word lines corresponding to one main word line are selected.

As described above, one memory array has a storage capacity of 4 K bits in the complementary bit line direction. However, if as many as 4K memory cells are connected to one complementary bit line, the parasitic capacitance of the complementary bit line increases, and a signal level that is read out cannot be obtained due to the capacitance ratio with a fine information storage capacitor. To
It is also divided into 16 in the complementary bit line direction. That is,
The complementary bit line is divided into 16 by the sense amplifier 16 indicated by a thick black line. Although not particularly limited, the sense amplifiers 16 are configured by a shared sense system, and are provided at both ends of the memory array.
Except for the above, complementary bit lines are provided on the left and right with respect to the sense amplifier 16, and are selectively connected to one of the left and right complementary bit lines.

FIG. 6 is a schematic layout diagram for explaining a dynamic RAM according to the present invention. The figure shows a schematic layout of the entire memory chip,
The layout of one memory array divided into eight is shown. This figure illustrates the embodiment of FIG. 5 from another point of view. That is, as in FIG. 5, the memory chip is located in the left and right and up and down directions with respect to the longitudinal direction (word line direction).
Each memory array is divided into four parts, and a plurality of bonding pads and indirect peripheral circuits (Bondin peripheral circuits) such as an address buffer, a control buffer, a predecoder, a timing control circuit, etc.
g Pad & perifheral Circuit).

Each of the two memory arrays has a storage capacity of about 8 Mbits. One of the two memory arrays is divided into eight in the word line direction as shown in an enlarged manner. A sub-array divided into 16 in the bit line direction is provided. On both sides of the sub-array in the bit line direction, sense amplifiers (Sence Amplifiers) are arranged in the bit line direction. A sub-word driver (Sub-Wo) is provided on both sides of the sub-array in the word line direction.
rd Driver) is placed.

The one array is provided with a total of 4096 word lines and 2048 pairs of complementary bit lines.
As a result, the storage capacity is about 8 Mbits in total. As described above, 4096 word lines are divided into 16 sub-arrays and arranged, so that one sub-array is provided with 256 word lines (sub-word lines). In addition, since 2048 pairs of complementary bit lines are divided into eight sub-arrays as described above, one sub-array is provided with 256 pairs of complementary bit lines.

At the center of the two arrays, a main row decoder is provided. That is, on the left side of the array shown in the figure, an array control circuit and a main word driver (Main Word driver) are provided corresponding to the main row decoder provided in common with the array provided on the right side. Is provided. The array control circuit includes a driver for driving the first sub-word selection line. A main word line extending so as to penetrate the eight divided sub-arrays is arranged in the array. The main word driver drives the main word line. Like the main word line, the first sub-word selection line is extended so as to pass through the eight divided sub-arrays. Above the array, a Y decoder (YDecoder) and a Y select line driver (YS
driver).

FIG. 7 is a schematic layout diagram showing one embodiment of a sub-array and its direct peripheral circuits in the dynamic RAM according to the present invention. FIG.
Are exemplarily shown as representatives of the four sub-arrays SBARY arranged at hatched positions in the memory array shown in FIG. By shading the region where the sub-array SBARY is formed, the sub-word driver region, the sense amplifier region, and the cross area provided around the region are distinguished.

The subarray SBARY is divided into the following four types. That is, when the extending direction of the word line is the horizontal direction, the first sub-array SBA
RY has 256 sub-word lines SWL and 256 complementary bit line pairs. Therefore, the above 2
The 256 sub-word drivers SWD corresponding to the 56 sub-word lines SWL are connected to the left and right of the sub-array by one.
It is divided into 28 pieces and arranged. The 256 sense amplifiers SA provided corresponding to the 256 pairs of complementary bit lines BL are of a shared sense amplifier type as described above, and are divided into 128 units above and below the sub-array.

As described above, the second sub-array SBARY arranged on the upper right has 256 sub-word lines SWL.
In addition to the book, eight spare word lines are provided. Therefore, the 264 sub-word drivers SWD corresponding to the above-mentioned 256 + 8 sub-word lines SWL are divided and arranged on the left and right of the sub-array in units of 132. As described above, the lower right sub-array has 256 pairs of complementary bit lines B
L, and 128 sense amplifiers are arranged vertically as described above. The 128 pairs of complementary bit lines formed in the upper and lower sub-arrays SBARY on the right side are commonly connected to the sense amplifier SA interposed therebetween via a shared switch MOSFET.

The third sub-array SBARY arranged at the lower left as described above is composed of 256 sub-word lines SWL, like the sub-array SBARY adjacent to the right.
As described above, 128 sub-word drivers are divided and arranged. The subarrays SBA arranged on the lower left and right sides
The 128 sub-word lines SWL of RY correspond to the 128 sub-word drivers SW formed in the region sandwiched between them.
D is commonly connected. The subarray SBARY arranged at the lower left as described above has four pairs of spare bit lines 4RE in addition to 256 pairs of normal complementary bit lines BL.
D is provided. Therefore, the 260 sense amplifiers SA corresponding to the 260 pairs of complementary bit lines BL are:
130 sub-arrays are divided and arranged above and below the sub-array.

As described above, the fourth sub-array SBARY arranged at the upper left has 256 regular sub-word lines SWL and eight spare sub-word lines R similarly to the right adjacent sub-array SBARY. Similarly, since four spare bit lines are provided in addition to the 256 normal complementary bit line pairs, the sub-word driver can
132 parts are arranged on the left and right sides, respectively.
A is arranged by dividing 130 vertically.

The main word lines MWL are extended as one of them is exemplarily shown as a representative. The column selection line YS is extended in the vertical direction in the figure as one of them is exemplarily shown as a representative. The main word line M
A sub-word line SWL is arranged in parallel with WL, and a complementary bit line BL (shown) is arranged in parallel with the column selection line YS. In this embodiment, although not particularly limited, the above-described four sub-arrays are used as a basic unit in FIG.
In the memory array for 8M bits as described above, eight sets of sub-arrays are formed in the bit line direction, and four sets of sub-arrays are formed in the word line direction. One set of 4 subarrays
Therefore, in the memory array of 8M bits, 8 × 4 × 4 = 128 sub-arrays are provided.
Since eight 8M-bit memory arrays are provided in the entire chip, 128 × 8 = 10 in the entire memory chip.
As many as 24 sub-arrays are formed.

Although not particularly limited, eight sub-word selection lines FX0B to FX0B to
FX7B has four sets (8) in the same manner as the main word line MWL.
) Of the sub-arrays. Four sub-word selection lines FX0B to FX3B and F
X4B to FX7B are separately extended on the upper and lower sub-arrays. The reason why one set of sub-word selection lines FX0B to FX7B are allocated to the two sub-arrays and they are extended on the sub-arrays is to reduce the memory chip size.

When the above-mentioned eight sub-word select lines FX0B to FX7B are allocated to each sub-array and are formed in the wiring channel on the sense amplifier area, as many as 16 sub-arrays as in the memory array of FIG. Since 32 memory arrays are arranged in total, 8 × 32 = 256 wiring channels are required. On the other hand, in the above-described embodiment, the wiring itself is connected to the two
Allocate sub word select lines FX0B to FX7B
Moreover, by arranging it so as to pass over the sub-array, it can be formed without providing a special wiring channel.

On the sub-array, one main word line is provided for eight sub-word lines, and a sub-word selection line is provided to select one of the eight sub-word lines. It is necessary. Since one main word line is formed for every eight sub word lines formed in accordance with the pitch of the memory cells, the wiring pitch of the main word lines is gentle. Therefore, it is relatively easy to form the sub-word selection line between the main word lines using the same wiring layer as the main word line.

The sub-word driver of this embodiment has a configuration in which one sub-word line SWL is selected by using a selection signal supplied through the sub-word selection line FX0B or the like and a selection signal obtained by inverting the selection signal as described later. take.
The sub-word driver employs a configuration in which the sub-word lines SWL of the sub-arrays arranged on the left and right of the sub-word driver are simultaneously selected. Therefore, as described above, for two sub-arrays, 128 × 2 = 2
The four sub-word selection lines are allocated and supplied to as many as 56 sub-word drivers. That is, focusing on the sub-word selection line FX0B, it is necessary to supply a selection signal to as many as 256 ÷ 4 = 64 sub-word drivers.

If the one extending in parallel with the main word line MWL is a first sub-word select line FX0B,
The six sub-word selection line driving circuits FXD which are provided in the upper left cross area and receive the selection signal from the first sub-word selection line FX0B are arranged in the above-mentioned vertical direction.
A second sub-word line FX0 that supplies a selection signal to the four sub-word drivers is provided. The first sub-word selection line FX0B extends in parallel with the main word line MWL and the sub-word line SWL, while the second sub-word selection line FX0B extends in parallel with the second sub-word selection line FX0B.
Of the sub-word selection line is orthogonal to the column selection line Y
S and the parallel bit line BL. For the eight first sub-word selection lines FX0B to FX7B, the second sub-word selection lines FX0 to FX7 are divided into even numbers FX0, 2, 4, 6 and odd numbers FX1, 3, 5, 7 Then, they are distributed to sub-word drivers SWD provided on the left and right of the sub-array SBARY.

The sub word select line driving circuit FXD is
In the same drawing, as shown by a triangle, two pieces are distributed above and below one cross area. That is, as described above, in the upper left cross area, the sub-word selection line driving circuit arranged on the lower side operates the first sub-word selection line F
Two sub-word selection line driving circuits FXD corresponding to X0B and provided in the cross area of the left middle part correspond to the first sub-word selection lines FX2B and FX4B, and are provided on the upper side provided in the lower left cross area. The arranged sub-word selection line driving circuit operates the first sub-word selection line FX.
6B.

In the cross area in the upper center, the sub word select line driving circuit arranged on the lower side corresponds to the first sub word select line FX1B, and the two sub word select line driving circuits provided in the cross area in the center middle part are driven. Circuit FXD
Correspond to the first sub-word selection lines FX3B and FX5B, and the upper sub-word selection line drive circuit provided in the cross area at the lower center corresponds to the first sub-word selection line FX7B. In the upper right cross area, the lower sub word select line drive circuit corresponds to the first sub word select line FX0B, and two sub word select line drive circuits provided in the right middle cross area. FXD corresponds to the first sub-word selection lines FX2B and FX4B, and the upper sub-word selection line driving circuit provided in the lower right cross area corresponds to the first sub-word selection line FX6B. As described above, the sub-word driver provided at the end of the memory array drives the sub-word line SWL only on the left side since there is no sub-array on the right side.

In the configuration in which the sub-word selection lines are arranged between the pitches of the main word lines on the sub-array as in this embodiment, a special wiring channel can be eliminated, so that 1
Even if eight sub-word selection lines are arranged in one sub-array, the memory chip does not become large. However, the sub-word selection line driving circuit F
The area is increased to form the XD, which hinders high integration. That is, in the cross area, a switch circuit IOS provided corresponding to the main input / output line MIO and the sub input / output line LIO as shown by the dotted line in FIG.
This is because there is no area allowance because peripheral circuits such as W, a power MOSFET for driving the sense amplifier, a drive circuit for driving the shared switch MOSFET, and a drive circuit for driving the precharge MOSFET are formed. The sub input / output line LIO and the main input / output line MIO
Is composed of a write-only line and a read-only line as described above.

As will be described later, in the sub-word driver, the second sub-word select lines FX0 to FX6 and the like
In parallel with this, a wiring for passing a selection signal corresponding to the first sub-word selection lines FX0B to FX6B is provided.
Since the load is small as described later, a special driver FXD like the second sub-word selection lines FX0 to FX6 is used.
, The first sub-word select line FX0B
To 6B are directly connected. However, the wiring layer is the second sub-word selection line FX0
The same thing as 6 is used.

Although not particularly limited, the second sub-word selection lines FX0 to FX0 corresponding to even numbers in the cross area
An N-channel type power MOSFET that supplies an internal voltage VDL that is a constant voltage to the sense amplifier as indicated by P in FIG.
T and a clamp voltage VDDC for overdrive as described later with respect to the sense amplifier as indicated by O in O.
P-channel type power MOSFET that supplies LP,
Also, as shown by N in the circle, an N-channel type power MOSFET for supplying the ground potential VSS of the circuit to the sense amplifier is provided.

Among the cross areas, those arranged in the extending direction B of the second sub-word selection lines FX0 to FX6 corresponding to the odd numbers include the precharge and equalization of the bit lines as indicated by B in ○. An N-channel drive MOSFET for turning off the MOSFET,
As shown by VBSG1 and VBG for the sense amplifier,
N-channel type power MOS for supplying SG2
An FET is provided. This N-channel type power MO
The SFET is an N-channel MOSFET amplifying MOSFET configured from both sides of the sense amplifier row.
It supplies the ground potential to the source of T. That is,
For 128 or 130 sense amplifiers provided in the sense amplifier area, an N-channel type power MOSFET provided in the cross area on the A side and two N MOSFETs provided in the cross area on the B side are provided. VBSG by both channel type power MOSFET
1 and VBSG2 are selectively supplied.

As described above, the sub-word line drive circuit SWD
Selects the sub-word lines of the sub-arrays on both sides with respect to the center. On the other hand, two sense amplifiers are activated corresponding to the selected sub-word lines of the two sub-arrays. That is, when the sub-word line is set to the selected state, the address selection MOSFET is turned on and the charge of the storage capacitor is combined with the bit line charge, so that the sense amplifier is activated to return to the original charge state. This is because a write operation needs to be performed.
For this reason, except for those corresponding to the subarrays at the ends, the power MOSFETs denoted by P, O and N
Is used to activate the sense amplifiers on both sides of it.

On the other hand, a sub-word line driving circuit SW provided on the right side of the sub-array provided at the end of the array
In D, only the sub-word lines of the sub-array are selected.
ET activates only the sense amplifier corresponding to the sub-array. The sense amplifier is of a shared sense type, and among the sub-arrays arranged on both sides of the shared amplifier, the shared switch MOSFE corresponding to the complementary bit line on the side where the sub-word line is not selected.
When T is turned off and disconnected, a read signal of the complementary bit line corresponding to the selected sub-word line is amplified, and a rewrite operation of returning the storage capacitor of the memory cell to the original charge state is performed.

FIG. 8 is a main part circuit diagram of another embodiment of the memory array section of the dynamic RAM according to the present invention. In the figure, one word line, a pair of complementary bit lines BL and / BL, and a sense amplifier and a precharge circuit, a read system circuit, a write system circuit, and the like associated therewith are illustratively shown. I have.

Dynamic memory cell (Memory Cell)
Is composed of an address selection MOSFET Qm and an information storage capacitor Cs in the same manner as described above. The gate of the address selection MOSFET Qm is connected to the word line WL, and one source and drain of the MOSFET Qm are connected to the bit line BL. The other source and drain are connected to the storage node of the information storage capacitor Cs. The other electrode of the information storage capacitor Cs is shared and supplied with a plate voltage.

The bit lines BL and / BL are arranged in parallel as shown in the figure, and are appropriately crossed as necessary to balance the bit line capacitance. The complementary bit lines BL and / BL are connected to the switch MOSFET Q1
And Q2 are connected to the input / output node of the sense amplifier. The sense amplifier has an N-channel MOSFET Q in which a gate and a drain are cross-connected and in a latch form.
5, Q6 and P-channel MOSFETs Q7, Q8. N-channel MOSFETs Q5 and Q6
Are connected to a common source line CSN. The sources of the P-channel MOSFETs Q7 and Q8 are connected to a common source line CSP. Although a common source line CSP is omitted in FIG.
A power switch MOSFET of T is provided, and the internal voltage VDL formed by the voltage generation circuit VDLG is supplied. An N-channel MOSFET (not shown) is also provided on the common source line CSN corresponding to the N-channel MOSFETs Q5 and Q6, and a voltage generation circuit VBSG
Internal voltage VBSG1 formed by 1G and VBSB2
And VBSG2 are selectively supplied.

The input / output node of the sense amplifier SA has a MOSFET Q11 for short-circuiting the complementary bit line,
The half precharge voltage VDL-VBS is applied to the complementary bit line.
Switch MOSFETs Q9 and Q11 that supply G2 / 2
Is provided. These MOs
The precharge signal PC is commonly supplied to the gates of the SFETs Q9 to Q11. The common source lines CSP and CSN of the sense amplifier SA are also connected to the common source lines C and CSN.
MOSFET Q27 for short-circuiting SP and CSN, and switch MOSF for supplying the half precharge voltage
A precharge circuit including ETQ25 and Q26 is provided. The gates of these MOSFETs Q25 to Q27 are commonly supplied with a precharge signal CSPC.

In this embodiment, in order to speed up the read operation as described above, a direct sense amplifier (hereinafter, referred to as a direct sense amplifier) is used.
Simply referred to as an amplifier circuit). The amplifying circuit includes differential amplifying MOSFETs Q12 and Q13 receiving the potential of the input / output node of the sense amplifier SA, and a MOSFET Q14 provided at a common source thereof to form an operating current.
Consists of The MOSFET Q14 receives the timing signal RS and the column selection signal YS at its source and gate, and enables the operation of the differential amplifier MOSFETs Q12 and Q13.

These amplification MOSFETs Q12 and Q13
Are connected to a read-only line RIO. The read-only line RIO includes MOSFETs Q19 to Q19.
21 is provided and the power supply voltage V
CC is precharged, one is pulled to a low level by the amplification operation of the differential amplification MOSFET, and the amplified signal is transmitted to the input of the main amplifier (Main Amp). The read-only line RIO is connected to the RIO
And / RIO.

By inserting such an amplifier circuit, the amplified signal of the sense amplifier SA becomes high level (VD
Despite having a relatively small signal amplitude such as L) and low level (VBSG1), a required signal level read signal can be transmitted to the main amplifier by amplifying in conjunction with the Y-system selection operation. Therefore, the reading time can be shortened.

In response to the provision of read-only line RIO as described above, write-only line WIO is provided. The high level and low level of the write signal transmitted from the write-only line WIO are changed to VDL and VB, respectively.
The voltage generation circuits VDLG and VBSG1 are shared to match SG1. That is, the write-only line WI
O is also provided with a precharge circuit similar to the above, comprising MOSFETs Q22 to Q24, and a write buffer (Writ
e Buffer), a write signal such as VDL and VBSG1 is transmitted.

When the write signal WEB0 is at a high level and W
If EB1 is at a low level, MOSFETs Q28 and Q30 are turned on, and a write signal is transmitted to write-only line WIO correspondingly. If the write signal WEB0 is low level and WEB1 is high level, MOSFET
Q29 and Q31 are turned on, and the corresponding write signal is transmitted to the write-only line WIO. The MOSFETs Q15 and Q16 are column selection switches, and are switch-controlled by the selection signal YS. The MOSFETs Q17 and Q18 provided in series with this are switch-controlled by the write pulse WP, during which a write signal such as VDL and VBSG1 transmitted to the write-only line WIO is applied to the input / output node of the sense amplifier SA. Tell

The MOSFETs Q1 and Q2 and Q3 and Q4
Is a shared switch MOSFET, and selects one of the memory mats provided on the left and right of the sense amplifier SA and the input / output circuit. When the left memory mat is selected, the MOSF is
ETQ1 and Q2 are kept on, the signal SHR is set to low level, and the bit line of the right memory mat is disconnected. When the right memory mat is selected, the MOSFETs Q3 and Q4 are kept on by the signal SHR, the signal SHL is set to low level, and the bit line of the left memory mat is disconnected. In the precharge period in which the memory access is completed, the signal SH
Both L and SHR go high, precharging both bit lines. The high level of the signals SHL and SHR is set to a high level like the boosted voltage VCH similarly to the word line WL.

FIG. 9 is a main block diagram for explaining the relationship between the main word lines and the sub word lines of the sub array. This figure mainly explains the circuit operation, and omits the geometrical arrangement of the sub-word selection lines as described above and collectively shows the sub-word selection lines FX0B to FX7B. In the figure, two main word lines MWL0 and MWL1 are shown as representatives for explaining the sub-word line selection operation. These main word lines MWL0 are selected by a main word driver MWD0. The other main word line MWL1 is similarly selected by a main word driver similar to the above.

The one main word line MWL0 has:
Eight sets of sub-word lines are provided in the extending direction. FIG. 2 exemplarily shows two sets of the sub-word lines as representatives. The sub word line is even 0 to
A total of eight sub-word lines 6 and odd numbers 1 to 7 are alternately arranged in one sub-array. Except for even numbers 0 to 6 adjacent to the main word driver and odd numbers 1 to 7 arranged on the far end side (opposite side of the word driver) of the main word line,
The sub-word driver arranged between the sub-arrays drives the sub-word lines of the left and right sub-arrays centered on the sub-word driver.

As a result, although the sub-array is divided into eight as described above, the sub-word driver SWD substantially selects the sub-word lines corresponding to the two sub-arrays at the same time. The sub-array is divided into four sets. As described above, the sub word line SWL is divided into even numbers 0 to 6 and even numbers 1 to 7,
Sub word drivers S are provided on both sides of each memory block.
In the configuration in which the WDs are arranged, the substantial pitch of the sub-word lines SWL arranged at high density in accordance with the arrangement of the memory cells can be relaxed twice in the sub-word driver SWD.
The sub-word driver SWD and the sub-word line SWL can be efficiently laid out on a semiconductor chip.

In this embodiment, the sub word driver SWD supplies a selection signal from the main word line MWL to four sub word lines 0 to 6 (1 to 7) in common. A sub-word select line FXB for selecting one sub-word line from the four sub-word lines is provided. The sub-word selection lines are composed of eight lines FXB0 to FXB7, of which even-numbered FXB0 to FXB6 are supplied to the even-numbered sub-word drivers 0 to 6, and odd-numbered FXB1 to FXB7 are odd-numbered sub-word drivers 1 to 7 of the odd-numbered columns. Supplied to Sub word select line FXB0
FXB7 to FXB7 are formed by a second-layer metal (metal) wiring layer M2 on the sub-array, and the main word lines MW similarly formed by the second-layer metal wiring layer M2.
It comprises a first sub-word selection line extending in parallel with L0 to MWLn and a second sub-word selection line extending in a direction orthogonal thereto. Although not particularly limited, the second sub-word selection line is formed by a third-layer metal wiring layer M3 so as to intersect with the main word line MWL.

The sub-word driver SWD has a main word line M as one of them is illustratively shown.
The input terminal is connected to WL, and the sub-word line S is connected to the output terminal.
A first CM including a P-channel MOSFET Q21 and an N-channel MOSFET Q22 to which WL is connected.
An OS inverter circuit and a switch MOSFET Q23 provided between the sub-word line SWL and the ground potential of the circuit and receiving the sub-word selection signal FXB. In order to connect the gate of this switch MOSFET Q23, a total of eight sub-word selection lines FX and FXB are arranged along a sub-word driver row consisting of 0, 2, 4, and 6, but in FIG. It is represented by one line.

A second CMOS inverter circuit N1 for forming an inverted signal FX of the sub-word selection signal FXB is provided as a sub-word selection line driving circuit FXD, and its output signal is used as an operating voltage terminal of the first CMOS inverter circuit. It is supplied to the source terminal of the P-channel MOSFET Q21. This second CMOS inverter circuit N
Although not particularly limited, 1 is formed in a cross area as shown in FIG. 3 and is commonly used in correspondence with a plurality (64 in the above embodiment) of sub-word drivers SWD.

In the above configuration of the sub-word driver SWD, when the main word line MWL is at a high level such as the boosted voltage VCH corresponding to the word line selection level, the N-channel type of the first CMOS inverter circuit The MOSFET Q22 is turned on, and the sub-word line SWL is set to a low level such as the ground potential of the circuit. At this time, the sub-word selection signal FXB becomes a selection level such as a low level such as the ground potential of the circuit, and the second CMOS as the sub-word selection line driving circuit FXD
Even if the output signal of the inverter circuit N1 is set to the selected level corresponding to the boosted voltage VCH, the main word line M
Depending on the non-selection level of WL, P-channel MOSFET
Since TQ21 is off, the sub word line SW
L is set to a non-selected state due to the ON state of the N-channel MOSFET Q22.

When the main word line MWL is at a low level such as the ground potential of the circuit corresponding to the selected level, the N-channel type MO of the first CMOS inverter circuit is
The SFET Q22 is turned off, and the P-channel type MO
SFET Q21 is turned on. At this time, if the sub-word selection signal FXB is at a low level such as the ground potential of the circuit, the output signal of the second CMOS inverter circuit N1 as the sub-word selection line driving circuit FXD is set to the selection level corresponding to the boosted voltage VCH. , The sub word line SWL is set to a selection level such as VCH. If,
If the sub-word selection signal FXB is at a non-selection level such as the boosted voltage VCH, the second CMOS inverter circuit N
2 becomes low level, and at the same time, N
The channel type MOSFET Q23 is turned on to set the sub-word line SWL to the low level non-selection level.

The main word line MWL and the first sub-word select line FXB arranged in parallel with the main word line MWL are both set to a non-selection level such as VCH as described above. Therefore, even when an insulation failure occurs between the main word line MWL and the first sub-word selection line FXB arranged in parallel when the RAM is in the non-selection state (standby) state, leakage current flows. There is no. As a result, the first sub-word selection line FXB can be formed between the main word lines MWL and arranged on the sub-array, and the DC failure due to the above-described leakage current can be avoided even when the layout density is increased. It will be reliable.

FIG. 10 is a main block diagram for explaining the relationship between the main word lines of the memory array and the sense amplifiers. In the figure, one main word line MWL is shown as a representative. This main word line MWL is selected by the main word driver MWD. Adjacent to the above main word driver,
Sub-word driver S corresponding to the even-numbered sub-word line
A WD is provided.

In the figure, although omitted, a complementary bit line (Pair Bit Line) is provided so as to be orthogonal to the sub-word line arranged in parallel with the main word line MWL. In this embodiment, although not particularly limited, the complementary bit lines are also divided into even columns and odd columns, and the sense amplifiers SA are distributed to the left and right corresponding to the respective sub-arrays (memory cell arrays). The sense amplifier SA is of the shared sense type as described above. In the sense amplifier SA at the end, although substantially one complementary bit line is not provided, the sense amplifier SA is connected to the complementary bit line via a shared switch MOSFET. Connected.

In the configuration in which the sense amplifiers SA are dispersedly arranged on both sides of the memory block as described above, since the complementary bit lines are distributed to the odd columns and the even columns, the pitch of the sense amplifier columns can be reduced. it can. In other words, it is possible to secure element areas for forming the sense amplifiers SA while arranging complementary bit lines at high density. The sub input / output lines are arranged along the arrangement of the sense amplifiers SA. This sub input / output line is connected to the complementary bit line via a column switch. Although a direct sense amplifier and a write circuit as described above are added to the column switch, in FIG.
OSFET is exemplified as a representative. The gate of the switch MOSFET is a column decoder COLUMN DECOR
It indicates that it is connected to the column selection line YS to which the DER selection signal is transmitted, and is actually constituted by the above-described read amplification circuit and write circuit.

FIG. 11 is a schematic block diagram showing one embodiment of the indirect peripheral circuit portion of the dynamic RAM according to the present invention. The timing control circuit TG receives a row address strobe signal / RA supplied from an external terminal.
S, column address strobe signal / CAS, write enable signal / WE and output enable signal /
In response to the OE, the operation mode is determined, and various timing signals necessary for the operation of the internal circuit are formed accordingly.
In this specification and the drawings, the symbol / is used to mean that the low level is the active level.

Signals R1 and R3 are row-related internal timing signals, and are used for row-related selection operations.
The timing signal φXL is a signal for taking in and holding a row-related address, and is supplied to the row address buffer RAB. That is, the row address buffer RAB
Is controlled by the address signal A0 by the timing signal φXL.
ＡAi are fetched and held in the latch circuit. The timing signal φYL is a signal for taking in and holding the column address, and is supplied to the column address buffer CAB. That is, the column address buffer RAB fetches an address input from the address terminals A0 to Ai in response to the timing signal φYL and causes the latch circuit to hold the address.

The signal φREF is a signal generated in the refresh mode, and is supplied to the multiplexer AMX provided at the input of the row address buffer.
In the refresh mode, control is performed so as to switch to the refresh address signal formed by the refresh address counter circuit RFC. The refresh address counter circuit RFC counts a refresh step pulse φRC formed by the timing control circuit TG to generate a refresh address signal. In this embodiment, an auto refresh and a self refresh as described later are provided. The timing signal φX is a word line selection timing signal, and is supplied to the decoder XIB, and based on the decoded signal of the lower 2 bits of the address signal, there are four types of word line selection timing signals Xi.
B is formed. The timing signal φY is a column selection timing signal, and is supplied to the column predecoder YPD to output the column selection signals AYix, AYjx, AYkx.

The timing signal φW is a control signal for instructing a write operation, and the timing signal φR is a control signal for instructing a read operation. These timing signals φW and φR are supplied to the input / output circuit I / O to activate an input buffer included in the input / output circuit I / O at the time of a write operation, thereby bringing the output buffer into an output high impedance state. On the other hand, at the time of the read operation, the output buffer is activated, and the input buffer is set to the output high impedance state. Timing signal φM
S is a signal that instructs, but is not limited to, a memory array selection operation, is supplied to a row address buffer RAB, and a selection signal MSi is output in synchronization with this timing. Timing signal φSA is a signal for instructing the operation of the sense amplifier. An activation pulse for the sense amplifier is formed based on the timing signal φSA.

In this embodiment, the row-related redundant circuit XR
ED is illustratively shown as a representative. That is, the circuit X-RED includes a storage circuit for storing a defective address and an address comparison circuit. The stored defective address is compared with the internal address signal BXi output from the row address buffer RAB, and when they do not match, the signal XE is set to the high level, and the signal XEB is set to the low level to enable the operation of the normal circuit. When the input internal address signal BXi matches the stored defective address, the signal XE is set to low level to inhibit the operation of selecting the defective main word line of the normal circuit, and the signal XEB is set to high level to set one signal. A selection signal XRiB for selecting a spare main word line is output.

The internal voltage generating circuit VG receives a power supply voltage VDD such as 3.3 V supplied from an external terminal and a ground potential VSS of 0 V, and is not particularly limited, but includes the boosted voltage VCH (+3.8 V), Internal voltage VDL (+2.2
V), plate voltage (precharge voltage) VPL (1.
35V), and the operating voltage VBSG1 (+
1.0 V), a voltage VBSG2 (+0.5 V) corresponding to the boosted ground level, and a substrate voltage VBB (-1.0 V) as necessary. The boosted voltage VCH
The substrate voltage VBB stably forms the voltages VCH and VBB using a charge pump circuit and its control circuit. The internal voltages VDL and VBSG1 and VBSG
2 is formed by internally lowering and stabilizing the power supply voltage VDD using a predetermined reference voltage. The plate voltage VPL and the half precharge voltage are equal to the internal step-down voltage VD.
It is formed by dividing the voltage of L and VBSG2 by half.

In a dynamic RAM having a large storage capacity as in this embodiment, the MOSFET formed therein is set to a low threshold voltage as the elements are miniaturized. The address selection MOSFET of the memory cell has a low threshold voltage, similarly to the MOSFET forming the peripheral circuit. As a result, the MOSFET forming the memory cell as in the conventional dynamic RAM is replaced with the M of the peripheral circuit.
It is not necessary to make the threshold voltage larger than that of the OSFET, and the manufacturing process can be simplified. Alternatively, by adopting the boosted ground sense method, the memory cell and the N-channel MOSFET of the peripheral circuit can be formed in the same P-type well region, so that high integration can be achieved.

N-channel type MO constituting memory cell
The SFET may be formed in a P-type well region in a deep N-type well region formed in a P-type substrate using a triple well structure. In this case, a substrate back-back voltage VBB is applied to the P-type well region to increase the effective threshold voltage of the address selection MOSFET and further reduce the sub-threshold leakage current flowing between the drain and the gate. It may be.

The operation and effect obtained from the above embodiment are as follows. That is, (1) In the BSG type dynamic RAM,
An internal voltage lower than the precharge voltage and higher than the boosted ground level is formed, and in the period before the word line is selected, the internal voltage is used as the low-level operation voltage of the sense amplifier, and the word line is not selected. Immediately before the state is changed, the internal voltage is switched to the boosted ground level and the low level of the bit line is set to the boosted ground level, thereby reducing the sub-threshold leakage current of the memory cell whose word line is not selected. On the other hand, there is an effect that high-speed operation can be realized by employing the direct sense amplifier.

(2) A pair of complementary bit lines are arranged in parallel as the bit lines, and the amplifying MOS of the sense amplifier is used.
The FET uses a shared method in which a read signal of a memory cell connected to one bit line is amplified using the precharge voltage of the other bit line as a reference voltage, and the precharge MOSFET and the column switch MOSFET are connected via a shared switch MOSFET. By providing the shared switch MOSFETs in common for the two sets of complementary bit lines and including these shared switch MOSFETs in the memory array, it is possible to obtain an effect that high integration can be achieved.

(3) The amplifying MOSFET constituting the sense amplifier is a CMOS latch circuit in which the input and output of two CMOS inverter circuits, which are a P-channel MOSFET and an N-channel MOSFET, are cross-connected. A power switch comprising a P-channel MOSFET for supplying the first internal voltage and an N-channel MOSFET for selectively supplying the second and third internal voltages to the latch circuit is provided. As a result, the effect that the bit line potential can be set with high sensitivity and with high accuracy can be obtained.

(4) The word line is composed of a main word line and a plurality of sub-word lines commonly assigned to the main word line, and the address of the dynamic memory cell is assigned to the sub-word line. The gate of the selection MOSFET is connected, and the sub-word line is
The sub-word driver receiving the signal of the main word line and the signal of the sub-word selection line causes one of the plurality of signals to be output.
One of them is selected, and by including such a sub-word driver in the memory array, it is possible to obtain an effect that high integration, high-speed operation, and high integration can be achieved while suppressing a sub-threshold leakage current.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, the configuration of the sub-array or the arrangement of a plurality of memory arrays mounted on a semiconductor chip can employ various embodiments according to the storage capacity and the like. In addition, the configuration of the sub-word driver can employ various embodiments. The portion of the input / output interface is a synchronous dynamic type R which operates in synchronization with a clock signal.
It may be AM, or may conform to the Rambus specification. The present invention can be widely used for a dynamic RAM.

[0094]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in the dynamic RAM of the BSG system, an internal voltage lower than the precharge voltage and higher than the boosted ground level is formed, and in the period before the word line is selected, the internal voltage is set as the low-level operating voltage of the sense amplifier. A voltage is used to switch the internal voltage to the boosted ground level and set the low level of the bit line to the boosted ground level immediately before the word line is set to the non-selected state. High-speed operation can be realized by employing a direct sense amplifier while reducing the sub-threshold leakage current of the memory cell.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram for explaining the present invention.

FIG. 2 is a circuit diagram showing one embodiment of a sense amplifier, a write circuit, and a read amplifier circuit in the dynamic RAM according to the present invention.

FIG. 3 is a schematic timing chart for explaining a read operation of the dynamic RAM according to the present invention;

FIG. 4 is a schematic timing chart for explaining a write operation of the dynamic RAM according to the present invention.

FIG. 5 is a layout diagram showing one embodiment of a dynamic RAM according to the present invention.

FIG. 6 is a schematic layout diagram for explaining a dynamic RAM according to the present invention.

FIG. 7 is a schematic layout diagram showing one embodiment of a sub-array and its direct peripheral circuits in a dynamic RAM according to the present invention.

FIG. 8 is a main part circuit diagram showing another embodiment of the memory array section of the dynamic RAM according to the present invention.

9 is a main part block diagram for explaining a relationship between a main word line and a sub word line of the sub array shown in FIG. 7;

10 is a main part block diagram for explaining a relationship between a main word line and a sense amplifier of the sub-array in FIG. 7;

FIG. 11 is a schematic block diagram showing one embodiment of an indirect peripheral circuit portion of a dynamic RAM according to the present invention.

[Explanation of symbols]

10: memory chip, 11: main row decoder area,
12: Main word driver area, 13: Column decoder area, 14: Peripheral circuit, bonding pad area, 1
5: Meseli cell array (sub array), 16: sense amplifier area, 17: sub word driver area, 18: cross area (cross area) SA: sense amplifier, SWD: sub word driver, M
WD: Main word driver, CTRL: Memory array control circuit, MWL0 to MWLn: Main word line, S
WL, SWL0 ... sub-word line, YS ... column select line,
SBARY: sub-array, TG: timing control circuit,
I / O: input / output circuit, RAB: row address buffer,
CAB: column address buffer, AMX: multiplexer, RFC: refresh address counter circuit, X
PD, YPD: Pretecoder circuit, X-DEC: Row system redundant circuit, XIB: Decoder circuit, Q1 to Q33: MO
SFET, RIO: read-only line, WIO: write-only line.

Claims (4)

[Claims] 1. An address selection MOSFET having a gate connected to a word line, one source and drain connected to a bit line crossing the word line, and the other source and drain connected to a storage node of a storage capacitor. A small voltage according to the information charge of the storage capacitor read to the bit line, a first internal voltage corresponding to a high level of the storage information, and a low level of the storage information,
A sense amplifier that operates at a second internal voltage higher than a ground potential and amplifies the voltage to the first or second internal voltage; and an intermediate voltage between the first and second internal voltages at the bit line. A precharge circuit for applying a precharge voltage corresponding to a voltage; a read amplifier circuit for receiving the amplified signal of the bit line and being activated by a bit line selection signal to transmit the amplified signal to a read-only line; A write circuit that receives a signal and is activated by a bit selection signal to transmit a write signal to the bit line. The sense amplifier comprises: And the third internal voltage lower than the precharge voltage and higher than the second internal voltage, and the bit line is connected to the first or third voltage. The third internal voltage is switched to the second internal voltage in a later period immediately before the word line is deselected, and the low level applied to the bit line is changed to the second level. A dynamic RAM characterized in that the RAM is changed in accordance with an internal voltage. 2. The bit line includes a pair of complementary bit lines arranged in parallel, and the amplification MOSFET of the sense amplifier transmits a read signal of a memory cell connected to one bit line to the other bit line. The precharge voltage is amplified as a reference voltage, and the shared switch M
The precharge circuit, the read amplifier circuit, and the write circuit are provided in common to the two sets of complementary bit lines via the OSFET. 2. The dynamic RAM according to claim 1, wherein the RAM is provided in common. 3. The sense amplifier comprises a P-channel MOSFET and an N-channel MOSFET.
A CMOS latch circuit in which the inputs and outputs of two CMOS inverter circuits made of ET are cross-connected; a P-channel MOSFET supplying the first internal voltage to the CMOS latch circuit; and a second internal voltage. 3. The dynamic RAM according to claim 1, further comprising a power switch circuit including an N-channel MOSFET for selectively supplying a third internal voltage. 4. A dynamic type comprising a plurality of word lines having a length divided in a direction in which a main word line extends and a plurality of word lines arranged in a bit line direction intersecting with the main word line. A sub-word line connected to the gate of an address selection MOSFET of a memory cell, extended so as to be parallel to the main word line;
A first sub-word selection line to which a selection signal for selecting one of a plurality of sub-word lines assigned to one main word line is transmitted; and a first sub-word selection line corresponding to the first sub-word selection line, A second sub-word select line extending orthogonal to the word line; a main word line select signal and a select signal transmitted through the second sub-word select line; A plurality of sub-word drivers, a plurality of sub-word lines, a plurality of sub-word lines, a plurality of sub-arrays including a plurality of complementary bit line pairs, and a plurality of dynamic memory cells provided at intersections thereof. The sub-word drivers are distributed and arranged at both ends of the sub-word line array composed of a plurality of Sense amplifiers are divided and arranged at both ends of a plurality of complementary bit line arrays of the sub-arrays, and the one sub-array is surrounded by the plurality of sub-word driver rows and the plurality of sense amplifier rows. A sub-common input / output line is provided corresponding to the sub-array, and a switch circuit connecting the common input / output line provided corresponding to the plurality of sub-arrays is provided at four corners of the sub-array, 4. The dynamic RAM according to claim 1, wherein the dynamic RAM is provided in a cross area where an amplifier and a sub-word driver intersect.